4 files changed, 16 insertions, 8 deletions

diff --git a/src/mainboard/intel/glkrvp/bootblock.c b/src/mainboard/intel/glkrvp/bootblock.c
index aeb4e894de..1bf1aa3aa6 100644
--- a/src/mainboard/intel/glkrvp/bootblock.c
+++ b/src/mainboard/intel/glkrvp/bootblock.c
@@ -16,7 +16,7 @@
 #include <baseboard/variants.h>
 #include <bootblock_common.h>
 #include <ec/ec.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc_lib.h>
 #include <soc/gpio.h>
 #include <variant/ec.h>
 
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
index 7cc2bbbc55..ff891a99a9 100644
--- a/src/mainboard/intel/glkrvp/ec.c
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -18,8 +18,8 @@
 #include <console/console.h>
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
+#include <intelblocks/lpc_lib.h>
 #include <rules.h>
-#include <soc/lpc.h>
 #include <variant/ec.h>
 
 static void ramstage_ec_init(void)
@@ -52,12 +52,14 @@ static void bootblock_ec_init(void)
 {
 	uint16_t ec_ioport_base;
 	size_t ec_ioport_size;
+
 	/*
 	 * Set up LPC decoding for the ChromeEC I/O port ranges:
 	 * - Ports 62/66, 60/64, and 200->208
 	 * - ChromeEC specific communication I/O ports.
 	 */
-	lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+	lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
+		| LPC_IOE_LGE_200);
 	google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
 	lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
 }
@@ -69,9 +71,15 @@ void mainboard_ec_init(void)
 			ramstage_ec_init();
 		else if (ENV_BOOTBLOCK)
 			bootblock_ec_init();
-	} else if (ENV_BOOTBLOCK)
-		lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 |
-			IOE_LGE_200);
+	} else if (ENV_BOOTBLOCK) {
+		/*
+		 * Set up LPC decoding for the ChromeEC I/O port ranges:
+		 * - Ports 62/66, 60/64, and 200->208
+		 * - ChromeEC specific communication I/O ports.
+		 */
+		lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
+			| LPC_IOE_LGE_200);
+	}
 
 	if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) {
 		printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
diff --git a/src/mainboard/intel/leafhill/bootblock.c b/src/mainboard/intel/leafhill/bootblock.c
index 3de44a8ff3..e35e8b8e7f 100644
--- a/src/mainboard/intel/leafhill/bootblock.c
+++ b/src/mainboard/intel/leafhill/bootblock.c
@@ -14,7 +14,7 @@
  */
 
 #include <bootblock_common.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc_lib.h>
 
 void bootblock_mainboard_init(void)
 {
diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c
index b8da814186..93236f029b 100644
--- a/src/mainboard/intel/minnow3/bootblock.c
+++ b/src/mainboard/intel/minnow3/bootblock.c
@@ -14,7 +14,7 @@
  */
 
 #include <bootblock_common.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc_lib.h>
 #include "gpio.h"
 
 void bootblock_mainboard_init(void)