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-rw-r--r--src/mainboard/intel/xe7501devkit/Kconfig33
-rw-r--r--src/mainboard/intel/xe7501devkit/acpi_tables.c89
-rw-r--r--src/mainboard/intel/xe7501devkit/board_info.txt1
-rw-r--r--src/mainboard/intel/xe7501devkit/bus.h16
-rw-r--r--src/mainboard/intel/xe7501devkit/devicetree.cb73
-rw-r--r--src/mainboard/intel/xe7501devkit/dsdt.asl16
-rw-r--r--src/mainboard/intel/xe7501devkit/fadt.c166
-rw-r--r--src/mainboard/intel/xe7501devkit/ioapic.h11
-rw-r--r--src/mainboard/intel/xe7501devkit/irq_tables.c74
-rw-r--r--src/mainboard/intel/xe7501devkit/mptable.c142
-rw-r--r--src/mainboard/intel/xe7501devkit/romstage.c76
11 files changed, 0 insertions, 697 deletions
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
deleted file mode 100644
index 923d39a645..0000000000
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-if BOARD_INTEL_XE7501DEVKIT
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_MPGA604
- select NORTHBRIDGE_INTEL_E7501
- select SOUTHBRIDGE_INTEL_I82870
- select SOUTHBRIDGE_INTEL_I82801CX
- select SUPERIO_SMSC_LPC47B272
- select ROMCC
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select UDELAY_TSC
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
- string
- default intel/xe7501devkit
-
-config MAINBOARD_PART_NUMBER
- string
- default "XE7501devkit"
-
-config IRQ_SLOT_COUNT
- int
- default 12
-
-config MAX_CPUS
- int
- default 2
-
-endif # BOARD_INTEL_XE7501DEVKIT
diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c
deleted file mode 100644
index fb7da1f8e7..0000000000
--- a/src/mainboard/intel/xe7501devkit/acpi_tables.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Ported to Intel XE7501DEVKIT from Agami Aruma
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- * (C) 2005 Digital Design Corporation
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <assert.h>
-#include "bus.h"
-#include "ioapic.h"
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- // Not implemented
- return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- // Not implemented
- return current;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int irq_start = 0;
- device_t dev = 0;
- struct resource* res = NULL;
-
-
- // SJM: Hard-code CPU LAPIC entries for now
- // Use SourcePoint numbering of processors
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
-
-
- // Southbridge IOAPIC
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, IO_APIC_ADDR, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // P64H2#2 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // P64H2#2 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-
- // P64H2#1 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // P64H2#1 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // Map ISA IRQ 0 to IRQ 2
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
-
- // IRQ9 differs from ISA standard - ours is active high, level-triggered
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
-
- return current;
-}
diff --git a/src/mainboard/intel/xe7501devkit/board_info.txt b/src/mainboard/intel/xe7501devkit/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/intel/xe7501devkit/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h
deleted file mode 100644
index 286120acf2..0000000000
--- a/src/mainboard/intel/xe7501devkit/bus.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef XE7501DEVKIT_BUS_H_INCLUDED
-#define XE7501DEVKIT_BUS_H_INCLUDED
-
-// These were determined by seeing how coreboot enumerates the various
-// PCI (and PCI-like) buses on the board.
-
-#define PCI_BUS_CHIPSET 0
-#define PCI_BUS_E7501_HI_B 1 // P64H2#2
-#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B
-#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A
-#define PCI_BUS_E7501_HI_D 4 // P64H2#1
-#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
-#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
-#define PCI_BUS_ICH3 7 // ICH3-S
-
-#endif // XE7501DEVKIT_BUS_H_INCLUDED
diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb
deleted file mode 100644
index 215ed97e56..0000000000
--- a/src/mainboard/intel/xe7501devkit/devicetree.cb
+++ /dev/null
@@ -1,73 +0,0 @@
-chip northbridge/intel/e7501
- device domain 0 on
- subsystemid 0x8086 0x2480 inherit
- device pci 0.0 on end # Chipset host controller
- device pci 0.1 on end # Host RASUM controller
- device pci 2.0 on # Hub interface B
- chip southbridge/intel/i82870 # P64H2
- device pci 1c.0 on end # IOAPIC - bus B
- device pci 1d.0 on end # Hub to PCI-B bridge
- device pci 1e.0 on end # IOAPIC - bus A
- device pci 1f.0 on end # Hub to PCI-A bridge
- end
- end
- device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
- device pci 4.0 on # Hub interface D
- chip southbridge/intel/i82870 # P64H2
- device pci 1c.0 on end # IOAPIC - bus B
- device pci 1d.0 on end # Hub to PCI-B bridge
- device pci 1e.0 on end # IOAPIC - bus A
- device pci 1f.0 on end # Hub to PCI-A bridge
- end
- end
- device pci 6.0 on end # E7501 Power management registers? (undocumented)
- chip southbridge/intel/i82801cx
- device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
- device pci 1d.1 off end # USB (not populated)
- device pci 1d.2 off end # USB (not populated)
- device pci 1e.0 on # Hub to PCI bridge
- device pci 0.0 on end
- end
- device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47b272
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # Keyboard interrupt
- irq 0x72 = 12 # Mouse interrupt
- end
- device pnp 2e.a off end # ACPI
- end
- end
- device pci 1f.1 on end # IDE
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # AC97 Audio
- device pci 1f.6 off end # AC97 Modem
- end # SB
- end # PCI domain
- device cpu_cluster 0 on
- chip cpu/intel/socket_mPGA604
- device lapic 0 on end
- end
- chip cpu/intel/socket_mPGA604
- device lapic 6 on end
- end
- end
-end
diff --git a/src/mainboard/intel/xe7501devkit/dsdt.asl b/src/mainboard/intel/xe7501devkit/dsdt.asl
deleted file mode 100644
index 87dd5744e3..0000000000
--- a/src/mainboard/intel/xe7501devkit/dsdt.asl
+++ /dev/null
@@ -1,16 +0,0 @@
-/* This is a dummy dsdt. Normal ACPI requires a DSDT, but in this case, ACPI
- is just a workaround for QNX. It would be nice to eventually have a real
- dsdt here.
- Note: It will not be hooked up at runtime. It won't even get linked.
- But we still need this file. */
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0
- "COREv2", // OEM id
- "COREBOOT", // OEM table id
- 0x20090419 // OEM revision
-)
-{
-}
diff --git a/src/mainboard/intel/xe7501devkit/fadt.c b/src/mainboard/intel/xe7501devkit/fadt.c
deleted file mode 100644
index 9707b9db11..0000000000
--- a/src/mainboard/intel/xe7501devkit/fadt.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT 0x0 /* ACPI mode only */
-#define CST_CONTROL 0x85
-#define PST_CONTROL 0x0
-#define ACPI_DISABLE 0xAA
-#define ACPI_ENABLE 0x55
-#define S4_BIOS 0x77
-#define GNVS_UPDATE 0xea
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
-
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 4;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 1;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 1;
- fadt->preferred_pm_profile = 0; /* PM_MOBILE; */
-
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = ACPI_ENABLE;
- fadt->acpi_disable = ACPI_DISABLE;
- fadt->s4bios_req = S4_BIOS;
- fadt->pstate_cnt = PST_CONTROL;
-
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = 0x0;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x28;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0; /* CST_CONTROL; */
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 85;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = 0x03;
-
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 0;
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 64;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h
deleted file mode 100644
index 9ac2aee3f8..0000000000
--- a/src/mainboard/intel/xe7501devkit/ioapic.h
+++ /dev/null
@@ -1,11 +0,0 @@
-// IOAPIC addresses determined by coreboot enumeration.
-// Someday add functions to get APIC IDs and versions from the chips themselves.
-
-#define IOAPIC_ICH3 2
-#define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010
-#define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010
-#define IOAPIC_P64H2_1_BUS_B 5 // IOAPIC 5 at 04:1c.0 MBAR = fe500000 DataAddr = fe500010
-#define IOAPIC_P64H2_1_BUS_A 8 // IOAPIC 8 at 04:1e.0 MBAR = fe501000 DataAddr = fe501010
-
-#define P64H2_IOAPIC_VERSION 0x20
-#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2
diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c
deleted file mode 100644
index 7af7a9f4f0..0000000000
--- a/src/mainboard/intel/xe7501devkit/irq_tables.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Run checkpir to verify any changes to this table...
- Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx
-*/
-
-#include <arch/pirq_routing.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include "bus.h"
-
-#define UNUSED_INTERRUPT {0, 0}
-#define PIRQ_A 0x60
-#define PIRQ_B 0x61
-#define PIRQ_C 0x62
-#define PIRQ_D 0x63
-#define PIRQ_E 0x68
-#define PIRQ_F 0x69
-#define PIRQ_G 0x6A
-#define PIRQ_H 0x6B
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes
- 0, // PCI bus number on which the interrupt router resides
- PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
- 0, // PCI-exclusive IRQ bitmap
- PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
- PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router
- 0, // Additional miniport information
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
- 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
- {
- // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
- // This was determined from linux-2.6.11/arch/x86/pci/irq.c
- // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
- // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
- // Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
-
- // INTA# INTB# INTC# INTD#
- // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
-
- {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
- {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1
-
- // P64H2#2 Bus A
- {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI
- // NOTE: Hotplug disabled on this bus
-
- // P64H2#2 Bus B
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23)
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24)
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 25, 0}, // Slot 2C (J25)
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 12, 0}, // Slot 2D (J12)
- // NOTE: Hotplug disabled on this bus
-
- // P64H2#1 Bus A
- {PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 20, 0}, // Slot 1A (J20)
- // NOTE: Hotplug disabled on this bus
-
- // P64H2#1 Bus B
- {PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet
- {PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21)
- // NOTE: Hotplug disabled on this bus
-
- // ICH-3 PCI bus
- {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video
- {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11)
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
deleted file mode 100644
index cc7eda5ddf..0000000000
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <assert.h>
-#include "bus.h"
-#include "ioapic.h"
-
-// Generate MP-table IRQ numbers for PCI devices.
-#define INT_A 0
-#define INT_B 1
-#define INT_C 2
-#define INT_D 3
-#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
-
-static int bus_isa;
-
-static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
-{
- device_t dev;
- struct resource *res;
-
- // TODO: Gack. This is REALLY ugly.
-
- // Southbridge IOAPIC
- smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, IO_APIC_ADDR); // APIC ID, Version, Address
-
- // P64H2#2 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
-
- // P64H2#2 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
-
-
- // P64H2#1 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
-
- // P64H2#1 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
- if (!dev)
- BUG();
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
-}
-
-static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
-{
- // Chipset PCI bus
- // Type Trigger | Polarity Bus ID IRQ APIC ID PIN#
- mptable_lintsrc(mc, PCI_BUS_CHIPSET);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_C), IOAPIC_ICH3, 18); // IDE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2
-
- // P64H2#2 Bus B
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)
-
- // P64H2#2 Bus A
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI
-
- // P64H2#1 Bus B
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)
-
- // P64H2#1 Bus A
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)
-
- // ICH-3
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11)
-
- // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
-
- mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0);
-}
-
-static void *smp_write_config_table(void* v)
-{
- struct mp_config_table *mc;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
- xe7501devkit_register_ioapics(mc);
- xe7501devkit_register_interrupts(mc);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
deleted file mode 100644
index e1a5807f28..0000000000
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include "southbridge/intel/i82801cx/early_smbus.c"
-#include "northbridge/intel/e7501/raminit.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/debug.c"
-#include "superio/smsc/lpc47b272/early_serial.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
-
-static void hard_reset(void)
-{
- outb(0x0e, 0x0cf9);
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/e7501/raminit.c"
-#include "northbridge/intel/e7501/reset_test.c"
-#include "lib/generic_sdram.c"
-
-// This function MUST appear last (ROMCC limitation)
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {
- .d0 = PCI_DEV(0, 0, 0),
- .d0f1 = PCI_DEV(0, 0, 1),
- .channel0 = { DIMM0, DIMM1, DIMM2, 0 },
- .channel1 = { DIMM4, DIMM5, DIMM6, 0 },
- },
- };
-
- if (bist == 0) {
- // Skip this if there was a built in self test failure
- early_mtrr_init();
- enable_lapic();
- }
-
- // Get the serial port running and print a welcome banner
- lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- // Halt if there was a built in self test failure
- report_bist_failure(bist);
-
- // print_pci_devices();
-
- // If this is a warm boot, some initialization can be skipped
-
- if (!bios_reset_detected())
- {
- enable_smbus();
- // dump_spd_registers(&memctrl[0]);
- // dump_smbus_registers();
- sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
- }
-
- // NOTE: ROMCC dies with an internal compiler error
- // if the following line is removed.
- print_debug("SDRAM is up.\n");
-}
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