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Diffstat (limited to 'src/mainboard/intel/tglrvp')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index b82f583c76..69ec54636c 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -68,7 +68,7 @@ chip soc/intel/tigerlake
register "TcssAuxOri" = "0"
# Enable S0ix
- register "s0ix_enable" = "1"
+ register "s0ix_enable" = "true"
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 51895b2c9d..fbb8418ff9 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -75,7 +75,7 @@ chip soc/intel/tigerlake
register "TcssAuxOri" = "0"
# Enable S0ix
- register "s0ix_enable" = "1"
+ register "s0ix_enable" = "true"
# Enable DPTF
register "dptf_enable" = "1"