diff options
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3')
3 files changed, 146 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc new file mode 100644 index 0000000000..23bf160883 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb new file mode 100644 index 0000000000..6a4bae894c --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -0,0 +1,78 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 08.0 off end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 off end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + device pci 13.0 off end # GSPI3 0xA0FD + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 15.0 on end # I2C0 0xA0E8 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + device pci 17.0 off end # SATA 0xA0D3 + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + device pci 1c.0 off end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 off end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 on end # RP10 0xA0B1 + device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1e.0 off end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 off end # GSPI0 0xA0AA + device pci 1e.3 off end # GSPI1 0xA0AB + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c new file mode 100644 index 0000000000..48ad36edb2 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ToDo: Fill gpio configuration */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* ToDo: Fill early gpio configurations for TPM and WWAN */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} |