diff options
Diffstat (limited to 'src/mainboard/intel/shadowmountain/variants')
4 files changed, 108 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc index a084537cb9..304ce1110d 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += early_gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 1b3e37537b..088b595e93 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -17,6 +17,28 @@ chip soc/intel/alderlake register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + register "PrmrrSize" = "0" + + # Enable PCH PCIE RP 5 using CLK 1 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR, + }" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h index dbd0e67887..2f7e85085a 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h @@ -16,4 +16,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); void variant_configure_early_gpio_pads(void); +const struct mb_cfg *variant_memory_params(void); +int variant_memory_sku(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/memory.c b/src/mainboard/intel/shadowmountain/variants/baseboard/memory.c new file mode 100644 index 0000000000..700e9c52cc --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/memory.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ CPU<>DRAM map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 10, 8, 9, 12, 15, 13, 14, 11, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 2, 6, 3, 7, 5, 1, 4, 0, }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 2, 0, 3, 1, 6, 4, 7, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 9, 10, 11, 13, 12, 14, 15, }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 1, 0, 3, 2, 6, 4, 5, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 8, 9, 15, 11, 14, 10, }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 8, 9, 11, 10, 13, 15, 14, 12, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 6, 5, 4, 7, 3, 2, 0, 1, }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 8, 13, 9, 12, 15, 11, 14, 10, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 2, 7, 3, 6, 5, 1, 4, 0, }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 0, 2, 1, 3, 6, 7, 4, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 15, 14, 10, 9, 8, 11, }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 8, 13, 9, 12, 15, 10, 14, 11, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 3, 6, 2, 7, 4, 1, 0, 5, }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 6, 1, 0, 7, 3, 2, 5, } /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 } /* DDR7_DQS[1:0] */ + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + .ccc_config = 0xD0, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPP_A7, + GPP_A20, + GPP_A19, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} |