3 files changed, 12 insertions, 8 deletions
diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c
index 45f39d46e2..46c2cdd6e0 100644
--- a/src/mainboard/intel/saddlebrook/romstage.c
+++ b/src/mainboard/intel/saddlebrook/romstage.c
@@ -49,8 +49,10 @@ void mainboard_memory_init_params(
 	* should be set in the FSP flash image and should not need to be
 	* changed.
 	*/
-	mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0);
-	mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0);
+	mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0,
+				   &memory_params->DqByteMapCh1);
+	mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0,
+				    &memory_params->DqsMapCpu2DramCh1);
 	mainboard_fill_rcomp_res_data(&memory_params->RcompResistor);
 	mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
 
diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h
index a5f1af3a77..70a1f68ce8 100644
--- a/src/mainboard/intel/saddlebrook/spd/spd.h
+++ b/src/mainboard/intel/saddlebrook/spd/spd.h
@@ -19,8 +19,8 @@
 
 #define RCOMP_TARGET_PARAMS	0x5
 
-void mainboard_fill_dq_map_data(void *dq_map_ptr);
-void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1);
+void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1);
 void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
 void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
 
diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c
index 5055d9a3af..a09cebcf4e 100644
--- a/src/mainboard/intel/saddlebrook/spd/spd_util.c
+++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c
@@ -17,7 +17,7 @@
 #include <string.h>
 #include "spd.h"
 
-void mainboard_fill_dq_map_data(void *dq_map_ptr)
+void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
 {
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
@@ -25,16 +25,18 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr)
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
 		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
 		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
-	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+	memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
+	memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
 }
 
-void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
 {
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
 		{ 0, 1, 3, 2, 4, 5, 6, 7 },
 		{ 1, 0, 4, 5, 2, 3, 6, 7 } };
-	memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+	memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
+	memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
 }
 
 void mainboard_fill_rcomp_res_data(void *rcomp_ptr)