diff options
Diffstat (limited to 'src/mainboard/intel/kunimitsu/romstage.c')
| -rw-r--r-- | src/mainboard/intel/kunimitsu/romstage.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 1d25c7fad9..84c2b6f534 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,10 +15,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> -#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> @@ -26,14 +23,6 @@ #include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { /* PCH_MEM_CFG[3:0] */ @@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params) GPIO_MEM_CONFIG_3, }; - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - - early_config_gpio(); - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */ |