diff options
Diffstat (limited to 'src/mainboard/intel/icelake_rvp/spd/spd_util.c')
| -rw-r--r-- | src/mainboard/intel/icelake_rvp/spd/spd_util.c | 107 |
1 files changed, 91 insertions, 16 deletions
diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index 25f7f20887..63b39fd3f4 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -13,11 +13,21 @@ * GNU General Public License for more details. */ #include <arch/byteorder.h> +#include <arch/cpu.h> #include <console/console.h> +#include <intelblocks/mp_init.h> #include <stdint.h> #include <string.h> +#include "../board_id.h" #include "spd.h" +enum icl_dimm_type { + icl_u_ddr4 = 0, + icl_u_lpddr4 = 1, + icl_u_lpddr4_type_3 = 4, + icl_y_lpddr4 = 6 +}; + void mainboard_fill_dq_map_ch0(void *dq_map_ptr) { /* DQ byte map Ch0 */ @@ -37,30 +47,61 @@ void mainboard_fill_dq_map_ch1(void *dq_map_ptr) memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } +static uint8_t get_spd_index(void) +{ + uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; + + return spd_index; +} + void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; - - const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; + const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; + const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; + const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case icl_u_lpddr4: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case icl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, + sizeof(dqs_map_u_lpddr_type_3)); + break; + case icl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } } void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; - - const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; + const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; + const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; - if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case icl_u_lpddr4: + case icl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case icl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -70,11 +111,45 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); } +/* + * get processor id using cpuid eax=1 + * return value will be in EAX register + */ +static uint32_t get_cpuid(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + + return cpuidr.eax; +} + void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { + 100, 33, 32, 33, 28 }; + static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { 80, 40, 40, 40, 30 }; + static const u16 RcompTarget_LPDDR4_Bx[RCOMP_TARGET_PARAMS] = { + 60, 20, 20, 20, 20 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(rcomp_strength_ptr, RcompTarget_DDR4, + sizeof(RcompTarget_DDR4)); + break; + case icl_y_lpddr4: + case icl_u_lpddr4: + case icl_u_lpddr4_type_3: + if (get_cpuid() == CPUID_ICELAKE_A0) + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, + sizeof(RcompTarget_LPDDR4_Ax)); + else + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx, + sizeof(RcompTarget_LPDDR4_Bx)); + break; + default: + break; + } } |