1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c
new file mode 100644
index 0000000000..36d6a3e6e2
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/mainboard.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
+
+static void mainboard_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
+
+static unsigned long mainboard_write_acpi_tables(struct device *device,
+						 unsigned long current,
+						 acpi_rsdp_t *rsdp)
+{
+	uintptr_t start_addr;
+
+	start_addr = current;
+
+	return start_addr;
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};