2 files changed, 18 insertions, 5 deletions
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 58732b11fb..2d0e2e1f44 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -7,12 +7,13 @@
 #include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
 		/* Recovery: GPIO22 */
-		{22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
+		{GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
 
 		/* Hard code the lid switch GPIO to open. */
 		{-1, ACTIVE_HIGH, 1, "lid"},
@@ -29,18 +30,18 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 int get_recovery_mode_switch(void)
 {
 	/* Recovery: GPIO22, active low */
-	return !get_gpio(22);
+	return !get_gpio(GPIO_REC_MODE);
 }
 
 int get_write_protect_state(void)
 {
 	/* Write protect is active low, so invert it here */
-	return !get_gpio(48);
+	return !get_gpio(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
 };
 
 void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h
new file mode 100644
index 0000000000..658ad83e19
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/onboard.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EMERALDLAKE2_ONBOARD_H
+#define EMERALDLAKE2_ONBOARD_H
+
+/* Recovery: GPIO22, active low */
+#define GPIO_REC_MODE	22
+
+/* Write protect is active low */
+#define GPIO_SPI_WP	48
+
+#endif