diff options
Diffstat (limited to 'src/mainboard/intel/emeraldlake2')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9308e9617a..a7ab4820a4 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -169,32 +169,32 @@ void main(unsigned long bist) u16 pm1_sts; struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, - ec_present: 0, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |