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-rw-r--r--src/mainboard/intel/dg43gt/Kconfig57
-rw-r--r--src/mainboard/intel/dg43gt/Kconfig.name2
-rw-r--r--src/mainboard/intel/dg43gt/Makefile.inc15
-rw-r--r--src/mainboard/intel/dg43gt/acpi/ec.asl1
-rw-r--r--src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl49
-rw-r--r--src/mainboard/intel/dg43gt/acpi/platform.asl28
-rw-r--r--src/mainboard/intel/dg43gt/acpi/superio.asl1
-rw-r--r--src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl91
-rw-r--r--src/mainboard/intel/dg43gt/acpi_tables.c38
-rw-r--r--src/mainboard/intel/dg43gt/board_info.txt6
-rw-r--r--src/mainboard/intel/dg43gt/cmos.default7
-rw-r--r--src/mainboard/intel/dg43gt/cmos.layout122
-rw-r--r--src/mainboard/intel/dg43gt/cstates.c21
-rw-r--r--src/mainboard/intel/dg43gt/devicetree.cb110
-rw-r--r--src/mainboard/intel/dg43gt/dsdt.asl43
-rw-r--r--src/mainboard/intel/dg43gt/gpio.c126
-rw-r--r--src/mainboard/intel/dg43gt/hda_verb.c53
-rw-r--r--src/mainboard/intel/dg43gt/romstage.c103
18 files changed, 873 insertions, 0 deletions
diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig
new file mode 100644
index 0000000000..d55f82dea5
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/Kconfig
@@ -0,0 +1,57 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_INTEL_DG43GT
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_X4X
+ select SOUTHBRIDGE_INTEL_I82801JX
+ select SUPERIO_WINBOND_W83627DHG
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_4096
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select INTEL_EDID
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+
+config VGA_BIOS_ID
+ string
+ default "8086,2e22"
+
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+config MAINBOARD_DIR
+ string
+ default "intel/dg43gt"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "DG43GT"
+
+config MAX_CPUS
+ int
+ default 4
+
+endif # BOARD_INTEL_DG43GT
diff --git a/src/mainboard/intel/dg43gt/Kconfig.name b/src/mainboard/intel/dg43gt/Kconfig.name
new file mode 100644
index 0000000000..73e73bf5f8
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_DG43GT
+ bool "DG43GT"
diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc
new file mode 100644
index 0000000000..630abda711
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/Makefile.inc
@@ -0,0 +1,15 @@
+#
+# This file is part of the coreboot project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ramstage-y += cstates.c
+romstage-y += gpio.c
diff --git a/src/mainboard/intel/dg43gt/acpi/ec.asl b/src/mainboard/intel/dg43gt/acpi/ec.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000000..19882b87d0
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+ Return (Package() {
+ /* PCI slot */
+ Package() { 0x0000ffff, 0, 0, 0x15},
+ Package() { 0x0000ffff, 1, 0, 0x16},
+ Package() { 0x0000ffff, 2, 0, 0x17},
+ Package() { 0x0000ffff, 3, 0, 0x14},
+
+ Package() { 0x0004ffff, 0, 0, 0x16},
+ Package() { 0x0004ffff, 1, 0, 0x17},
+ Package() { 0x0004ffff, 2, 0, 0x14},
+ Package() { 0x0004ffff, 3, 0, 0x15},
+
+ Package() { 0x0006ffff, 0, 0, 0x17},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+ Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+ })
+}
diff --git a/src/mainboard/intel/dg43gt/acpi/platform.asl b/src/mainboard/intel/dg43gt/acpi/platform.asl
new file mode 100644
index 0000000000..6c92a4ed47
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice. */
+ Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
+}
diff --git a/src/mainboard/intel/dg43gt/acpi/superio.asl b/src/mainboard/intel/dg43gt/acpi/superio.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
new file mode 100644
index 0000000000..510af9abb6
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for x4x */
+/* Uses reset defaults + some undocumented device taken from vendor DSDT*/
+
+/* PCI Interrupt Routing */
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ /* PEG */
+ Package() { 0x0001ffff, 0, 0, 0x10 },
+ /* Internal GFX */
+ Package() { 0x0002ffff, 0, 0, 0x10 },
+ /* ME */
+ Package() { 0x0003ffff, 0, 0, 0x10 },
+ Package() { 0x0003ffff, 1, 0, 0x11 },
+ Package() { 0x0003ffff, 2, 0, 0x12 },
+ /* ?? */
+ Package() { 0x0016ffff, 0, 0, 0x12 },
+ Package() { 0x0016ffff, 1, 0, 0x13 },
+ /* GBE 0:19.0 */
+ Package() { 0x0019ffff, 0, 0, 0x10 },
+ /* USB and EHCI */
+ Package() { 0x001affff, 0, 0, 0x10 },
+ Package() { 0x001affff, 1, 0, 0x11 },
+ Package() { 0x001affff, 2, 0, 0x12 },
+ /* High Definition Audio 0:1b.0 */
+ Package() { 0x001bffff, 0, 0, 0x10 },
+ /* PCIe Root Ports 0:1c.x */
+ Package() { 0x001cffff, 0, 0, 0x10 },
+ Package() { 0x001cffff, 1, 0, 0x11 },
+ Package() { 0x001cffff, 2, 0, 0x12 },
+ Package() { 0x001cffff, 3, 0, 0x13 },
+ /* USB and EHCI 0:1d.x */
+ Package() { 0x001dffff, 0, 0, 0x10 },
+ Package() { 0x001dffff, 1, 0, 0x11 },
+ Package() { 0x001dffff, 2, 0, 0x12 },
+ Package() { 0x001dffff, 3, 0, 0x13 },
+ /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */
+ Package() { 0x001fffff, 1, 0, 0x11 },
+ })
+ } Else {
+ Return (Package() {
+ /* PEG */
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* Internal GFX */
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* ME */
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* GBE */
+ Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* USB */
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ /* High Definition Audio 0:1b.0 */
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ /* PCIe Root Ports 0:1c.x */
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* USB and EHCI 0:1d.x */
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ /* PATA/SATA/SMBUS 0:1f.1-3 */
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c
new file mode 100644
index 0000000000..b96c1b965f
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi_tables.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/ioapic.h>
+
+#include "southbridge/intel/i82801jx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+
+ gnvs->pwrs = 1; /* Power state (AC = 1) */
+ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
+ gnvs->apic = 1; /* Enable APIC */
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->cmap = 0x01; /* Enable COM 1 port */
+}
diff --git a/src/mainboard/intel/dg43gt/board_info.txt b/src/mainboard/intel/dg43gt/board_info.txt
new file mode 100644
index 0000000000..b74a33cf77
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/dg43gt/cmos.default b/src/mainboard/intel/dg43gt/cmos.default
new file mode 100644
index 0000000000..9a61c07a94
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Disable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout
new file mode 100644
index 0000000000..e5e2a97609
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/cmos.layout
@@ -0,0 +1,122 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 10 sata_mode
+409 2 e 7 power_on_after_fail
+411 1 e 1 nmi
+
+# coreboot config options: cpu
+#424 8 r 0 unused
+
+# coreboot config options: northbridge
+432 4 e 11 gfx_uma_size
+#435 549 r 0 unused
+
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+1024 144 r 0 recv_enable_results
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+10 0 AHCI
+10 1 Compatible
+11 0 1M
+11 1 4M
+11 2 8M
+11 3 16M
+11 4 32M
+11 5 48M
+11 6 64M
+11 7 128M
+11 8 256M
+11 9 96M
+11 10 160M
+11 11 224M
+11 12 352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/intel/dg43gt/cstates.c b/src/mainboard/intel/dg43gt/cstates.c
new file mode 100644
index 0000000000..aa7214dcb3
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/cstates.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <southbridge/intel/i82801jx/i82801jx.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
new file mode 100644
index 0000000000..6421673825
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -0,0 +1,110 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host Bridge
+ device pci 2.0 on end # Integrated graphics controller
+ device pci 2.1 on end # Integrated graphics controller 2
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801jx # Southbridge
+ register "gpe0_en" = "0x40"
+
+ # Set AHCI mode.
+ register "sata_port_map" = "0x1f"
+ register "sata_clock_request" = "0"
+ register "sata_traffic_monitor" = "0"
+
+ # Enable PCIe ports 0,2,3 as slots.
+ register "pcie_slot_implemented" = "0xb"
+
+ device pci 19.0 on end # GBE
+ device pci 1a.0 on end # USB
+ device pci 1a.1 on end # USB
+ device pci 1a.2 on end # USB
+ device pci 1a.7 on end # USB
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 off end # PCIe 2
+ device pci 1c.2 on end # PCIe 3
+ device pci 1c.3 on end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/winbond/w83627dhg # Super I/O
+ device pnp 2e.0 on # Floppy
+ # GLOBAL
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 5
+ drq 0x74 = 4
+ end
+ device pnp 2e.2 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM 2
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ irq 0x70 = 1
+ io 0x62 = 0x64
+ irq 0xf0 = 0x85
+ end
+ device pnp 2e.6 off end # SPI
+ device pnp 2e.7 on # GPIO 6
+ irq 0x30 = 0x06
+ end
+ device pnp 2e.8 off end # WDTO# PLED
+ device pnp 2e.9 on # GPIO 2,3,4,5
+ irq 0x30 = 0x0a
+ end
+ device pnp 2e.a on # ACPI
+ irq 0xe4 = 0x30 # power dram during S3
+ end
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290
+ end
+ device pnp 2e.c off end # PECI, SST
+ end
+ end
+ device pci 1f.1 on end # PATA/IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMbus
+ device pci 1f.4 off end
+ device pci 1f.5 on end # IDE
+ device pci 1f.6 off end
+ end
+ end
+end
diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl
new file mode 100644
index 0000000000..d2b9f30b33
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/i82801jx/i82801jx.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // global NVS and variables
+ #include "acpi/platform.asl"
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801jx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/dg43gt/gpio.c b/src/mainboard/intel/dg43gt/gpio.c
new file mode 100644
index 0000000000..69cd10a764
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/gpio.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio11 = GPIO_LEVEL_LOW,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = { };
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_HIGH,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = { };
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = { };
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = { };
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+
+};
diff --git a/src/mainboard/intel/dg43gt/hda_verb.c b/src/mainboard/intel/dg43gt/hda_verb.c
new file mode 100644
index 0000000000..e9b1fae1f9
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/hda_verb.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0888,
+ 0x80860028, // Subsystem ID
+ 14, // Number of entries
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x11, 0x01452140),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19960),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214520),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4006f601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x99430130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ /* HDMI */
+ 0x80862803,
+ 0x80860101,
+ 1,
+
+ AZALIA_PIN_CFG(0, 0x03, 0x18560010)
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
new file mode 100644
index 0000000000..5b9816345d
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801jx/i82801jx.h>
+#include <southbridge/intel/common/gpio.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+#include <superio/winbond/common/winbond.h>
+#include <lib.h>
+#include <northbridge/intel/x4x/iomap.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+/* Early mainboard specific GPIO setup.
+ * We should use standard gpio.h eventually
+ */
+
+static void mb_gpio_init(void)
+{
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+ pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
+
+ setup_pch_gpios(&mainboard_gpio_map);
+
+ /* Set default GPIOs on superio: TODO (here or in ramstage) */
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+ RCBA8(0x31ff);
+
+ RCBA32(0x3410) = 0x00060464;
+ RCBA32(0x3414) = 0x00000020;
+ RCBA32(0x3418) = 0x01320001;
+ RCBA32(0x341c) = 0xbf7f001f;
+ RCBA32(0x3430) = 0x00000002;
+ RCBA32(0x3f00) = 0x0000000b;
+}
+
+static void ich10_enable_lpc(void)
+{
+ /* Configure serial IRQs.*/
+ pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
+ pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
+ pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601);
+ pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291);
+ pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
+ u8 boot_path = 0;
+ u8 s3_resume;
+
+ /* Disable watchdog timer */
+ RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
+
+ /* Set southbridge and Super I/O GPIOs. */
+ ich10_enable_lpc();
+ mb_gpio_init();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+
+ x4x_early_init();
+
+ s3_resume = southbridge_detect_s3_resume();
+ if (s3_resume)
+ boot_path = BOOT_PATH_RESUME;
+ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
+ boot_path = BOOT_PATH_WARM_RESET;
+
+ printk(BIOS_DEBUG, "Initializing memory\n");
+ sdram_initialize(boot_path, spd_addrmap);
+ quick_ram_check();
+ printk(BIOS_DEBUG, "Memory initialized\n");
+
+ x4x_late_init(s3_resume);
+
+ printk(BIOS_DEBUG, "x4x late init complete\n");
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 07:39:30 +0000