diff options
Diffstat (limited to 'src/mainboard/intel/dg43gt/early_init.c')
| -rw-r--r-- | src/mainboard/intel/dg43gt/early_init.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/intel/dg43gt/early_init.c b/src/mainboard/intel/dg43gt/early_init.c new file mode 100644 index 0000000000..8457707ba1 --- /dev/null +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <northbridge/intel/x4x/x4x.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) + +void bootblock_mainboard_early_init(void) +{ + RCBA32(0x3410) = 0x00060464; + RCBA32(RCBA_BUC) &= ~BUC_LAND; + RCBA32(0x3418) = 0x01320001; + RCBA32(0x341c) = 0xbf7f001f; + RCBA32(0x3430) = 0x00000002; + RCBA32(0x3f00) = 0x0000000b; + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} |