diff options
Diffstat (limited to 'src/mainboard/intel/dg41wv/romstage.c')
| -rw-r--r-- | src/mainboard/intel/dg41wv/romstage.c | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index a6969ad4d2..c0127b6c45 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -56,19 +56,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); - /* Fixed IO decode ranges */ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - /* LPC enable devices */ - pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - /* IO decode range: HWM on 0xa00 */ - pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -77,7 +64,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |