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-rw-r--r--src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl2
-rw-r--r--src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl2
-rw-r--r--src/mainboard/intel/d945gclf/acpi/mainboard.asl2
-rw-r--r--src/mainboard/intel/d945gclf/acpi/platform.asl8
-rw-r--r--src/mainboard/intel/d945gclf/acpi/thermal.asl2
-rw-r--r--src/mainboard/intel/d945gclf/acpi_tables.c2
-rw-r--r--src/mainboard/intel/d945gclf/chip.h2
-rw-r--r--src/mainboard/intel/d945gclf/cmos.layout2
-rw-r--r--src/mainboard/intel/d945gclf/devicetree.cb6
-rw-r--r--src/mainboard/intel/d945gclf/dsdt.asl2
-rw-r--r--src/mainboard/intel/d945gclf/mainboard_smi.c2
-rw-r--r--src/mainboard/intel/d945gclf/mptable.c2
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c12
-rw-r--r--src/mainboard/intel/d945gclf/rtl8168.c2
14 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
index 93e4b87fee..de2ec481fb 100644
--- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
+++ b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* This is board specific information: IRQ routing for the
+/* This is board specific information: IRQ routing for the
* i945
*/
diff --git a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
index b3b60d6ece..931fbfdeb4 100644
--- a/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* This is board specific information: IRQ routing for the
+/* This is board specific information: IRQ routing for the
* 0:1e.0 PCI bridge of the ICH7
*/
diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl
index 3d1ad0ea29..d321771c0a 100644
--- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl
+++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl
@@ -28,7 +28,7 @@ Device (SLPB)
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
-
+
// Wake
Name(_PRW, Package(){0x1d, 0x04})
}
diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl
index 7c5b9da429..0a7930a3cc 100644
--- a/src/mainboard/intel/d945gclf/acpi/platform.asl
+++ b/src/mainboard/intel/d945gclf/acpi/platform.asl
@@ -42,9 +42,9 @@ Method(TRAP, 1, Serialized)
Return (SMIF) // Return value of SMI handler
}
-/* The _PIC method is called by the OS to choose between interrupt
+/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
- *
+ *
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
@@ -74,12 +74,12 @@ Method(_WAK,1)
// Notify PCI Express slots in case a card
// was inserted while a sleep state was active.
- // Are we going to S3?
+ // Are we going to S3?
If (LEqual(Arg0, 3)) {
// ..
}
- // Are we going to S4?
+ // Are we going to S4?
If (LEqual(Arg0, 4)) {
// ..
}
diff --git a/src/mainboard/intel/d945gclf/acpi/thermal.asl b/src/mainboard/intel/d945gclf/acpi/thermal.asl
index fb9d940955..fc79a35f61 100644
--- a/src/mainboard/intel/d945gclf/acpi/thermal.asl
+++ b/src/mainboard/intel/d945gclf/acpi/thermal.asl
@@ -25,7 +25,7 @@ Scope (\_TZ)
{
// FIXME these could/should be read from the
- // GNVS area, so they can be controlled by
+ // GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x04)
Name(TC2V, 0x03)
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index b7f92114c5..afa695502f 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/intel/d945gclf/chip.h b/src/mainboard/intel/d945gclf/chip.h
index 90e8c27999..4e1432de69 100644
--- a/src/mainboard/intel/d945gclf/chip.h
+++ b/src/mainboard/intel/d945gclf/chip.h
@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout
index e99c43d79b..9997584a54 100644
--- a/src/mainboard/intel/d945gclf/cmos.layout
+++ b/src/mainboard/intel/d945gclf/cmos.layout
@@ -1,6 +1,6 @@
#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2007-2008 coresystems GmbH
#
# This program is free software; you can redistribute it and/or
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index af5f22b302..01a0bc67a5 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -1,6 +1,6 @@
##
## This file is part of the coreboot project.
-##
+##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
@@ -25,7 +25,7 @@ chip northbridge/intel/i945
end
end
- device pci_domain 0 on
+ device pci_domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller
@@ -66,7 +66,7 @@ chip northbridge/intel/i945
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
- #device pci 1e.2 off end # AC'97 Audio
+ #device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47m15x
diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl
index 1b025994f0..bf57e74b21 100644
--- a/src/mainboard/intel/d945gclf/dsdt.asl
+++ b/src/mainboard/intel/d945gclf/dsdt.asl
@@ -34,7 +34,7 @@ DefinitionBlock(
// General Purpose Events
//#include "acpi/gpe.asl"
-
+
// mainboard specific devices
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/intel/d945gclf/mainboard_smi.c b/src/mainboard/intel/d945gclf/mainboard_smi.c
index fc4c508194..c07a24c399 100644
--- a/src/mainboard/intel/d945gclf/mainboard_smi.c
+++ b/src/mainboard/intel/d945gclf/mainboard_smi.c
@@ -23,7 +23,7 @@
#include <cpu/x86/smm.h>
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
-/* The southbridge SMI handler checks whether gnvs has a
+/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
extern global_nvs_t *gnvs;
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 5d57f3d743..62850ebf1c 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
/* Legacy Interrupts */
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index e3e5814d3e..45e9fb1341 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -1,6 +1,6 @@
/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
@@ -105,7 +105,7 @@ static void ich7_enable_lpc(void)
static void early_superio_config_lpc47m15x(void)
{
device_t dev;
-
+
dev=PNP_DEV(0x2e, LPC47M15X_SP1);
pnp_enter_conf_state(dev);
@@ -276,7 +276,7 @@ void main(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-
+
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
@@ -286,8 +286,8 @@ void main(unsigned long bist)
/* Perform some initialization that must run before stage2 */
early_ich7_init();
- /* This should probably go away. Until now it is required
- * and mainboard specific
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
*/
rcba_config();
@@ -331,7 +331,7 @@ void main(unsigned long bist)
* memory completely, but that's a wonderful clean up task for another
* day.
*/
- if (resume_backup_memory)
+ if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
diff --git a/src/mainboard/intel/d945gclf/rtl8168.c b/src/mainboard/intel/d945gclf/rtl8168.c
index e278bcfb4e..04fd56ccb1 100644
--- a/src/mainboard/intel/d945gclf/rtl8168.c
+++ b/src/mainboard/intel/d945gclf/rtl8168.c
@@ -28,7 +28,7 @@
static void nic_init(struct device *dev)
{
printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
- // Nothing to do yet, but this has to be here to keep
+ // Nothing to do yet, but this has to be here to keep
// coreboot from trying to execute an option ROM.
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-28 00:55:23 +0000