diff options
Diffstat (limited to 'src/mainboard/intel/d945gclf/Config.lb')
| -rw-r--r-- | src/mainboard/intel/d945gclf/Config.lb | 237 |
1 files changed, 237 insertions, 0 deletions
diff --git a/src/mainboard/intel/d945gclf/Config.lb b/src/mainboard/intel/d945gclf/Config.lb new file mode 100644 index 0000000000..384fc399ba --- /dev/null +++ b/src/mainboard/intel/d945gclf/Config.lb @@ -0,0 +1,237 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +## +## Only use the option table in a normal image +## +default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE + +## +## Image size calculation +## + +include /config/nofailovercalculation.lb + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o +driver rtl8168.o +if CONFIG_GENERATE_MP_TABLE object mptable.o end +if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end + +if CONFIG_GENERATE_ACPI_TABLES + object fadt.o + object acpi_tables.o + makerule dsdt.c + depends "$(CONFIG_MAINBOARD)/dsdt.asl" + action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" + action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" + action "mv $(CURDIR)/dsdt.hex dsdt.c" + end + object ./dsdt.o +end + +object reset.o + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" +end + +else + +makerule ./auto.inc + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" +end + +end + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + ldscript /cpu/x86/car/cache_as_ram.lds +end + +## +## Build our reset vector (This is where coreboot is entered) +## +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +## +## Setup Cache-As-Ram +## +mainboardinit cpu/intel/model_106cx/cache_as_ram.inc + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +end + +### +### O.k. We aren't just an intermediary anymore! +### + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/i945 + + device apic_cluster 0 on + chip cpu/intel/socket_441 + device apic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 01.0 off end # i945 PCIe root port + chip drivers/pci/onboard + device pci 02.0 on end # vga controller + # register "rom_address" = "0xfffc0000" # 256 KB image + # register "rom_address" = "0xfff80000" # 512 KB image + # register "rom_address" = "0xfff00000" # 1 MB image + end + device pci 02.1 on end # display controller + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x07" + register "pirqc_routing" = "0x05" + register "pirqd_routing" = "0x07" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x06" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "gpe0_en" = "0x20000601" + + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe + #device pci 1c.3 off end # PCIe port 4 + #device pci 1c.4 off end # PCIe port 5 + #device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge + #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m15x + device pnp 2e.0 off # Floppy + end + device pnp 2e.3 off # Parport + end + device pnp 2e.4 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + end + device pnp 2e.7 on # Keyboard+Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 # HW accel A20. + end + device pnp 2e.8 on # GAME + # all default + end + device pnp 2e.a on # PME + end + device pnp 2e.b on # MPU + end + end + end + #device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + #device pci 1f.4 off end # Realtek ID Codec + end + end +end |