diff options
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb | 100 |
1 files changed, 59 insertions, 41 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9115fd93f6..4a2fad9540 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -6,31 +6,48 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" + register "RMT" = "1" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC7)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC7)" - register "PchHdaDspEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -46,13 +63,25 @@ chip soc/intel/cannonlake register "PcieRpEnable[11]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[17]" = "1" + register "PcieRpEnable[18]" = "1" + register "PcieRpEnable[19]" = "1" + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "0x6" + register "PcieClkSrcUsage[4]" = "0x18" + register "PcieClkSrcUsage[5]" = "14" + register "PcieClkSrcUsage[8]" = "0x40" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -60,15 +89,14 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" + # HECI + register "HeciEnabled" = "1" device domain 0 on device pci 00.0 on end # Host Bridge @@ -79,29 +107,19 @@ chip soc/intel/cannonlake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on end # CNVi wifi device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0001"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "hid_desc_reg_offset" = "0x1" - device i2c 2C on end - end - end # I2C 0 + device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 @@ -128,9 +146,9 @@ chip soc/intel/cannonlake end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 on end # GbE end end |