diff options
Diffstat (limited to 'src/mainboard/intel/baskingridge/chromeos.c')
| -rw-r--r-- | src/mainboard/intel/baskingridge/chromeos.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index b6c41640ac..d4408f4d06 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -7,12 +7,13 @@ #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -32,18 +33,18 @@ int get_recovery_mode_switch(void) * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return get_gpio(69); + return get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(22); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) |