diff options
Diffstat (limited to 'src/mainboard/intel/amenia/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/amenia/dsdt.asl | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl new file mode 100644 index 0000000000..ba4e7226fc --- /dev/null +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + } + } + /* Mainboard Specific devices */ + #include "acpi/mainboard.asl" + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} |