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Diffstat (limited to 'src/mainboard/intel/amenia/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/amenia/dsdt.asl | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl deleted file mode 100644 index ab922abc25..0000000000 --- a/src/mainboard/intel/amenia/dsdt.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - /* global NVS and variables */ - #include <soc/intel/apollolake/acpi/globalnvs.asl> - - /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> - #include <soc/intel/apollolake/acpi/pch_hda.asl> - } - } - - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - /* Mainboard Specific devices */ - #include "acpi/mainboard.asl" - - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> - - #include "acpi/superio.asl" - - Scope (\_SB) { - /* Dynamic Platform Thermal Framework */ - #include "acpi/dptf.asl" - } -} |