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Diffstat (limited to 'src/mainboard/intel/adlrvp')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb8
-rw-r--r--src/mainboard/intel/adlrvp/gpio.c4
2 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 80edb92003..f2f768a8be 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -51,6 +51,12 @@ chip soc/intel/alderlake
register "PcieClkSrcUsage[5]" = "0x5"
register "PcieRpClkReqDetect[5]" = "1"
+ # Enable PCH PCIE RP 8 using free running CLK (0x80)
+ register "PcieRpEnable[7]" = "1"
+ register "PcieClkSrcClkReq[7]" = "7"
+ register "PcieClkSrcUsage[7]" = "0x80"
+ register "PcieRpClkReqDetect[7]" = "1"
+
# Enable PCH PCIE RP 9 using CLK 1
register "PcieRpEnable[8]" = "1"
register "PcieClkSrcClkReq[1]" = "1"
@@ -245,7 +251,7 @@ chip soc/intel/alderlake
device pci 1c.4 on end # RP5
device pci 1c.5 on end # RP6
device pci 1c.6 off end # RP7
- device pci 1c.7 off end # RP8
+ device pci 1c.7 on end # RP8
device pci 1d.0 on end # RP9
device pci 1d.1 off end # RP10
device pci 1d.2 on end # RP11
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 89e6f5826b..4cb8c3a06c 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -72,6 +72,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_B4, 1, PLTRST),
/* M.2_PCH_SSD_PWREN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+ /* SRCCLK_OEB7 */
+ PAD_CFG_GPO(GPP_A7, 0, PLTRST),
+ /* SRCCLK_OEB6 */
+ PAD_CFG_GPO(GPP_E5, 0, PLTRST),
/* M.2_SSD_PDET_R */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),