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-rw-r--r--src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index 818f32f9fa..73055010ca 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -13,8 +13,6 @@ chip soc/intel/alderlake
register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration
- # Enable Speed Shift Technology/HWP support
- register "speed_shift_enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2