diff options
Diffstat (limited to 'src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb')
-rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 274 |
1 files changed, 0 insertions, 274 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb deleted file mode 100644 index ce55fa3914..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ /dev/null @@ -1,274 +0,0 @@ -chip soc/intel/alderlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_E" - - # FSP configuration - - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "gen4_dec" = "0x000c0081" - - register "PrmrrSize" = "0" - - # Enable PCH PCIE RP 5 using CLK 2 - register "PcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcUsage[2]" = "0x4" - register "PcieRpClkReqDetect[4]" = "1" - - # Enable PCH PCIE RP 6 using CLK 5 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcUsage[5]" = "0x5" - register "PcieRpClkReqDetect[5]" = "1" - - # Enable PCH PCIE RP 9 using CLK 1 - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcUsage[1]" = "0x8" - register "PcieRpClkReqDetect[8]" = "1" - - # Enable PCH PCIE RP 11 for optane - register "PcieRpEnable[10]" = "1" - # Hybrid storage mode - register "HybridStorageMode" = "1" - - # Enable CPU PCIE RP 1 using PEG CLK 0 - register "PcieClkSrcUsage[0]" = "0x40" - - # Enable PCU PCIE PEG Slot 1 and 2 - register "PcieClkSrcUsage[3]" = "0x41" - register "PcieClkSrcUsage[4]" = "0x42" - - # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below - register "PcieClkSrcUsage[6]" = "0xff" - - register "SataSalpSupport" = "1" - - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - register "SataPortsDevSlp" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - # Enable EDP in PortA - register "DdiPortAConfig" = "1" - register "DdiPortBConfig" = "1" - - # TCSS USB3 - register "TcssAuxOri" = "0" - - register "s0ix_enable" = "1" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - [PchSerialIoIndexGSPI3] = 0, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - [PchSerialIoIndexGSPI3] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSndwEnable[0]" = "1" - register "PchHdaAudioLinkSndwEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" - - # Intel Common SoC Config - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 on end # PEG60 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 - device pci 08.0 off end # GNA - device pci 09.0 off end # NPK - device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 on end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 on end # TBT DMA1 - device pci 0e.0 off end # VMD - device pci 10.0 off end - device pci 10.1 off end - device pci 10.2 on end # CNVi: BT - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end - device pci 12.0 off end # SensorHUB - device pci 12.5 off end - device pci 12.6 off end # GSPI2 - device pci 13.0 off end # GSPI3 - device pci 13.1 off end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.9 on end - end - end - end - end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI - device pci 14.2 off end # Shared RAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi: WiFi - device pci 15.0 on end # I2C0 - device pci 15.1 on end # I2C1 - device pci 15.2 on end # I2C2 - device pci 15.3 on end # I2C3 - device pci 16.0 on end # HECI1 - device pci 16.1 off end # HECI2 - device pci 16.2 off end # CSME - device pci 16.3 off end # CSME - device pci 16.4 off end # HECI3 - device pci 16.5 off end # HECI4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C4 - device pci 19.1 on end # I2C5 - device pci 19.2 off end # UART2 - device pci 1c.0 on end # RP1 - device pci 1c.1 off end # RP2 - device pci 1c.2 off end # RP3 - device pci 1c.3 off end # RP4 - device pci 1c.4 on end # RP5 - device pci 1c.5 on end # RP6 - device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 - device pci 1d.0 on end # RP9 - device pci 1d.1 off end # RP10 - device pci 1d.2 on end # RP11 - device pci 1d.3 off end # RP12 - device pci 1e.0 on end # UART0 - device pci 1e.1 off end # UART1 - device pci 1e.2 on end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1f.0 on end # eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # PMC - device pci 1f.3 on - chip drivers/intel/soundwire - device generic 0 on - chip drivers/soundwire/alc711 - # SoundWire Link 0 ID 1 - register "desc" = ""Headset Codec"" - device generic 0.1 on end - end - end - end - end # Intel Audio SNDW - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI - device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH - end -end |