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Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 95b006e2f6..a6bad136b6 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -83,7 +83,7 @@ chip soc/intel/alderlake
}"
# Hybrid storage mode
- register "hybrid_storage_mode" = "1"
+ register "hybrid_storage_mode" = "true"
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{