diff options
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 41cf33747e..68c0754bd6 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -1,5 +1,14 @@ chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -137,14 +146,14 @@ chip soc/intel/alderlake register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "serial_io_gspi_cs_mode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -172,6 +181,10 @@ chip soc/intel/alderlake # Intel Common SoC Config register "common_soc_config" = "{ + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -429,6 +442,14 @@ chip soc/intel/alderlake device ref uart0 on end device ref gspi0 on end device ref p2sb on end + device ref gspi1 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + device spi 0 on end + end + end device ref hda on chip drivers/intel/soundwire device generic 0 on |