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-rw-r--r--src/mainboard/hp/dl165_g6_fam10/Kconfig65
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/Kconfig.name2
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/Makefile.inc14
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/board_info.txt3
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/bootblock.c69
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/cmos.layout101
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/devicetree.cb88
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c85
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/irq_tables.c55
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h37
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/mptable.c164
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/romstage.c240
12 files changed, 0 insertions, 923 deletions
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig
deleted file mode 100644
index 65d7edfd90..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_HP_DL165_G6_FAM10
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select CPU_AMD_SOCKET_F_1207
- select NORTHBRIDGE_AMD_AMDFAM10
- select SOUTHBRIDGE_BROADCOM_BCM21000
- select SOUTHBRIDGE_BROADCOM_BCM5785
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_SERVERENGINES_PILOT
- select SUPERIO_NSC_PC87417
- select DIMM_DDR2
- select DIMM_REGISTERED
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select ENABLE_APIC_EXT_ID
-
-config MAINBOARD_DIR
- string
- default hp/dl165_g6_fam10
-
-config DCACHE_RAM_BASE
- hex
- default 0xc4000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x0c000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "ProLiant DL165 G6 (Fam10)"
-
-config MAX_CPUS
- int
- default 12
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x6
-
-config IRQ_SLOT_COUNT
- int
- default 15
-
-config BOOTBLOCK_MAINBOARD_INIT
- string
- default "mainboard/hp/dl165_g6_fam10/bootblock.c"
-
-endif # BOARD_HP_DL165_G6_FAM10
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig.name b/src/mainboard/hp/dl165_g6_fam10/Kconfig.name
deleted file mode 100644
index ceb6e86b14..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_HP_DL165_G6_FAM10
- bool "ProLiant DL165 G6 Fam10"
diff --git a/src/mainboard/hp/dl165_g6_fam10/Makefile.inc b/src/mainboard/hp/dl165_g6_fam10/Makefile.inc
deleted file mode 100644
index 0fd5b079f5..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/Makefile.inc
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/hp/dl165_g6_fam10/board_info.txt b/src/mainboard/hp/dl165_g6_fam10/board_info.txt
deleted file mode 100644
index 30851bc699..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: server
-Board URL: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c01765799
-Release year: 2009
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
deleted file mode 100644
index b70b0a3e24..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pnp_ops.h>
-#include <device/pnp_def.h>
-
-#define SCH4307_CONFIG_PORT 0x162e
-static inline void shc4307_enter_ext_func_mode(pnp_devfn_t dev)
-{
- unsigned int port = dev >> 8;
- outb(0x55, port);
-}
-
-static inline void shc4307_exit_ext_func_mode(pnp_devfn_t dev)
-{
- unsigned int port = dev >> 8;
- outb(0xaa, port);
-}
-
-#define CMOS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x6)
-#define KBD_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x7)
-#define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3)
-#define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa)
-
-/* FIXME: This appears to be a super-io initialisation,
- * placed in the mainboard directory.
- */
-void shc4307_init(void)
-{
- shc4307_enter_ext_func_mode(CMOS_DEV);
- pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */
- pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70);
- pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72);
- pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8);
- /* pnp_set_enable(CMOS_DEV, 3); */
- pnp_write_config(CMOS_DEV, 0x30, 3);
-
- pnp_set_logical_device(KBD_DEV); /* Keyboard */
- pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1);
- pnp_set_enable(KBD_DEV, 1);
-
- pnp_set_logical_device(DBG_DEV); /* Debug */
- pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80);
- pnp_set_enable(DBG_DEV, 1);
-
- pnp_set_logical_device(REGS_DEV);
- pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600);
- pnp_set_enable(REGS_DEV, 1);
-
- shc4307_exit_ext_func_mode(CMOS_DEV);
-}
-
-static void bootblock_mainboard_init(void)
-{
- bootblock_northbridge_init();
- bootblock_southbridge_init();
- shc4307_init();
-}
diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout
deleted file mode 100644
index 40d93aa5d6..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout
+++ /dev/null
@@ -1,101 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-393 3 r 0 unused
-#394 7 unused
-401 1 e 1 interleave_chip_selects
-402 1 e 1 interleave_nodes
-403 1 e 1 interleave_memory_channels
-404 2 e 8 max_mem_clock
-406 1 e 2 multi_core
-412 4 e 6 debug_level
-416 5 e 10 ecc_scrub_rate
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 gart
-456 1 e 1 ECC_memory
-457 1 e 1 ECC_redirection
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Information
-6 7 Debug
-6 8 Spew
-8 0 DDR2-800
-8 1 DDR2-667
-8 2 DDR2-533
-8 3 DDR2-400
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-10 0 Disabled
-10 1 40ns
-10 2 80ns
-10 3 160ns
-10 4 320ns
-10 5 640ns
-10 6 1.28us
-10 7 2.56us
-10 8 5.12us
-10 9 10.2us
-10 10 20.5us
-10 11 41us
-10 12 81.9us
-10 13 163.8us
-10 14 327.7us
-10 15 655.4us
-10 16 1.31ms
-10 17 2.62ms
-10 18 5.24ms
-10 19 10.49ms
-10 20 20.97sms
-10 21 42ms
-10 22 84ms
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb
deleted file mode 100644
index 4e08efd401..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb
+++ /dev/null
@@ -1,88 +0,0 @@
-chip northbridge/amd/amdfam10/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_F_1207
- device lapic 0 on end
- end
- end
- device domain 0 on
- chip northbridge/amd/amdfam10 # northbridge
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # devices on link 2
- chip southbridge/broadcom/bcm21000 # HT2100
- device pci 0.0 on
- end # bridge to slot PCI-E 4x ??
- device pci 1.0 on
- end
- device pci 2.0 on
- end # unused
- device pci 3.0 on # bridge to slot PCI-E 16x ??
- end
- device pci 4.0 on
- end # unused
- device pci 5.0 on
- device pci 4.0 on end # BCM5715 NIC
- device pci 4.1 on end # BCM5715 NIC
- end
- end
- chip southbridge/broadcom/bcm5785 # HT1000
- device pci 0.0 on # HT PXB 0x0036
- device pci d.0 on end # PCI/PCI-X bridge 0x0104
- device pci e.0 on end # SATA 0x024a
- end
- device pci 1.0 on end # Legacy pci main 0x0205
- device pci 1.1 on end # IDE 0x0214
- device pci 1.2 on # LPC 0x0234
- chip superio/nsc/pc87417
- device pnp 4e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 4e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 4e.2 off # Com 2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 4e.3 off # Com 1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.4 off end # SWC
- device pnp 4e.5 off end # Mouse
- device pnp 4e.6 off # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 4e.7 off end # GPIO
- device pnp 4e.f off end # XBUS
- device pnp 4e.10 on #RTC
- io 0x60 = 0x70
- io 0x62 = 0x72
- end
- end # end superio
- end # end pci 1.2
- device pci 1.3 off end # WDTimer 0x0238
- device pci 1.4 on end # XIOAPIC0 0x0235
- device pci 1.5 on end # XIOAPIC1
- device pci 1.6 on end # XIOAPIC2
- device pci 2.0 on end # USB 0x0223
- device pci 2.1 on end # USB
- device pci 2.2 on end # USB
- device pci 3.0 on end # VGA
- end
- end
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- end # amdfam10
-
- end #domain
-end
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
deleted file mode 100644
index 0d8ee8c28b..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-void get_bus_conf(void)
-{
-
- unsigned int apicid_base;
-
- struct device *dev;
- int i;
- struct mb_sysconf_t *m;
-
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
- memset(m, 0, sizeof(struct mb_sysconf_t));
-
- get_default_pci1234(32);
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
-
- m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff;
- m->bus_bcm5780[0] = m->bus_bcm5785_0;
-
- /* bcm5785 */
- printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0);
- dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
- if (dev) {
- printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev));
- m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1);
- dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
- printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev));
- if (dev)
- m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn);
- }
-
- /* bcm5780 */
- for (i = 1; i < 6; i++) {
- dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
- if (dev)
- m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- else
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
- }
-
-/*I/O APICs: APIC ID Version State Address*/
- apicid_base = 0x10;
- for (i = 0; i < 3; i++)
- m->apicid_bcm5785[i] = apicid_base+i;
-}
diff --git a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c
deleted file mode 100644
index ef52ef8b50..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifdef GETPIR
-#include "pirq_routing.h"
-#else
-#include <arch/pirq_routing.h>
-#endif
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32 + 16 * 11, /* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x02 << 3) | 0x0, /* Interrupt router dev */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x1166, /* Vendor */
- 0x36, /* Device */
- 0, /* Miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xe9, /* Checksum (has to be set to some value that
- * would give 0 after the sum of all bytes
- * for this structure (including checksum).
- */
- {
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x01, (0x0e << 3) | 0x0, {{0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}}, 0x0, 0x0}, /* 1166:024a */
- {0x00, (0x03 << 3) | 0x0, {{0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}}, 0x0, 0x0}, /* 1166:0223 */
- {0x00, (0x06 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x0, 0x0}, /* 1166:0140 */
- {0x00, (0x07 << 3) | 0x0, {{0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */
- {0x00, (0x08 << 3) | 0x0, {{0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */
- {0x00, (0x09 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */
- {0x00, (0x0a << 3) | 0x0, {{0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */
- {0x02, (0x02 << 3) | 0x0, {{0x28, 0xdac0}, {0x27, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 14e4:1648 */
- {0x06, (0x00 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x2, 0x0},
- {0x03, (0x00 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x2, 0x0},
- {0x07, (0x00 << 3) | 0x0, {{0x2a, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 102b:0522 */
- }
-};
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h b/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h
deleted file mode 100644
index b2a11e33f2..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_bcm5780[7];
- unsigned char bus_bcm5785_0;
- unsigned char bus_bcm5785_1;
- unsigned char bus_bcm5785_1_1;
- unsigned int apicid_bcm5785[3];
-
- unsigned int sbdn2;
-};
-
-#endif
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
deleted file mode 100644
index 6bf83cf928..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com>
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <device/pci.h>
-#include <stdint.h>
-#if CONFIG(LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- struct mb_sysconf_t *m;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- m = sysconf.mb;
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /*I/O APICs: APIC ID Version State Address*/
- {
- struct device *dev = NULL;
- int i;
- struct resource *res;
- for (i = 0; i < 3; i++) {
- dev = dev_find_device(0x1166, 0x0235, dev);
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- }
-
- /* IRQ routing as factory BIOS */
- outb(0x00, 0xc00); outb(0x09, 0xc01);
- outb(0x01, 0xc00); outb(0x0a, 0xc01);
- outb(0x02, 0xc00); outb(0x0e, 0xc01);
- outb(0x03, 0xc00); outb(0x07, 0xc01);
- outb(0x07, 0xc00); outb(0x05, 0xc01);
-
- // 8259 registers...
- outb(0xa0, 0x4d0);
- outb(0x0e, 0x4d1);
-
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x0205, 0);
- if (dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
- pci_write_config32(dev, 0x64, dword);
- }
- // set GEVENT pins to NO OP
- /* outb(0x33, 0xcd6); outb(0x00, 0xcd7);
- outb(0x34, 0xcd6); outb(0x00, 0xcd7);
- outb(0x35, 0xcd6); outb(0x00, 0xcd7); */
- }
-
- // hide XIOAPIC PCI configuration space
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x205, 0);
- if (dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 26);
- pci_write_config32(dev, 0x64, dword);
- }
- }
-
- mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
-
- /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1, 0xe, 0, m->apicid_bcm5785[0], 0x5);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x3, 0, m->apicid_bcm5785[0], 0xa);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x6, 0, m->apicid_bcm5785[2], 0x4);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x7, 0, m->apicid_bcm5785[2], 0x3);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x8, 0, m->apicid_bcm5785[2], 0x2);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0x9, 0, m->apicid_bcm5785[2], 0x1);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_0, 0xa, 0, m->apicid_bcm5785[2], 0x0);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 0, m->apicid_bcm5785[2], 0x8);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5785_1_1, 0x2, 1, m->apicid_bcm5785[2], 0x7);
- smp_write_pci_intsrc(mc, mp_INT, m->bus_bcm5780[5], 0x0, 0, m->apicid_bcm5785[2], 0xa);
-
- /* enable int */
- /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
- {
- struct device *dev;
- dev = dev_find_device(0x1166, 0x0205, 0);
- if (dev) {
- uint32_t dword;
- dword = pci_read_config32(dev, 0x6c);
- dword |= (1 << 4); // enable interrupts
- printk(BIOS_DEBUG, "6ch: %x\n",dword);
- pci_write_config32(dev, 0x6c, dword);
- }
- }
-
- /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- //extended table entries
- smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
- smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
- smp_write_bus_hierarchy(mc, 8, 0x01, 0);
- smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
- smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
-
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
deleted file mode 100644
index 1b91e97ec7..0000000000
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Tyan
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include <console/console.h>
-#include <timestamp.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <spd.h>
-#include <delay.h>
-#include <superio/serverengines/pilot/pilot.h>
-#include <superio/nsc/pc87417/pc87417.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <southbridge/amd/common/reset.h>
-#include "southbridge/broadcom/bcm5785/early_smbus.c"
-#include "southbridge/broadcom/bcm5785/early_setup.c"
-
-#include "cpu/amd/quadcore/quadcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
-#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
- u8 val;
- outb(0x3d, 0x0cd6);
- outb(0x87, 0x0cd7);
-
- outb(0x44, 0xcd6);
- val = inb(0xcd7);
- outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
-}
-
-inline int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-static const u8 spd_addr[] = {
- // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
- //first node
- RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#endif
-};
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = get_sysinfo();
- u32 bsp_apicid = 0, val;
- msr_t msr;
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- /* mov bsp to bus 0xff when > 8 nodes */
- set_bsp_node_CHtExtNodeCfgEn();
- enumerate_ht_chain();
- bcm5785_enable_lpc();
- pc87417_enable_dev(RTC_DEV); /* Enable RTC */
- }
-
- post_code(0x30);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
-
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- update_microcode(val);
-
- post_code(0x33);
-
- cpuSetAMDMSR(0);
- post_code(0x34);
-
- amd_ht_init(sysinfo);
- post_code(0x35);
-
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
-
- post_code(0x36);
-
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fixup prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
-
- wait_all_core0_started();
-
-#if CONFIG(LOGICAL_CPUS)
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores(bsp_apicid);
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
-#if CONFIG(SET_FIDVID)
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
- /* FIXME: The sb fid change may survive the warm reset and only
- * need to be done once.*/
-
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
- post_code(0x39);
-
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
-
- post_code(0x3A);
-
- /* show final fid and vid */
- msr = rdmsr(MSR_COFVID_STS);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-#endif
-
- init_timer();
-
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- printk(BIOS_INFO, "...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset - shouldn't see this message!!!\n");
- }
-
- /* It's the time to set ctrl in sysinfo now; */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus();
-
- //do we need ACPI timer, tsc...., only debug need it for better output
- /* all ap stopped? */
-// init_timer(); // Need to use TMICT to synchronize FID/VID
-
- timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
- raminit_amdmct(sysinfo);
- timestamp_add_now(TS_AFTER_INITRAM);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- amdmct_cbmem_store_info(sysinfo);
-
- bcm5785_early_setup();
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- * This routine is called every time a non-coherent chain is processed.
- * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- * swap list. The first part of the list controls the BUID assignment and the
- * second part of the list provides the device to device linking. Device orientation
- * can be detected automatically, or explicitly. See documentation for more details.
- *
- * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- * based on each device's unit count.
- *
- * Parameters:
- * @param[in] node = The node on which this chain is located
- * @param[in] link = The link on the host for this chain
- * @param[out] List = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
- /* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
- printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
- if ((node == 0) && (link == 0)) { /* BSP SB link */
- *List = swaplist;
- return 1;
- }
- }
-
- return 0;
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 04:10:10 +0000