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-rw-r--r--src/mainboard/hp/dl145_g1/acpi_tables.c4
-rw-r--r--src/mainboard/hp/dl145_g1/fadt.c12
-rw-r--r--src/mainboard/hp/dl145_g1/get_bus_conf.c4
-rw-r--r--src/mainboard/hp/dl145_g1/irq_tables.c2
-rw-r--r--src/mainboard/hp/dl145_g1/romstage.c30
-rw-r--r--src/mainboard/hp/dl145_g3/get_bus_conf.c6
-rw-r--r--src/mainboard/hp/dl145_g3/irq_tables.c74
-rw-r--r--src/mainboard/hp/dl145_g3/mptable.c38
-rw-r--r--src/mainboard/hp/dl145_g3/romstage.c22
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c6
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/mptable.c30
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/romstage.c2
12 files changed, 115 insertions, 115 deletions
diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c
index c85f380bf0..47e0a3ab8c 100644
--- a/src/mainboard/hp/dl145_g1/acpi_tables.c
+++ b/src/mainboard/hp/dl145_g1/acpi_tables.c
@@ -25,7 +25,7 @@
unsigned long acpi_fill_madt(unsigned long current)
{
- unsigned int gsi_base=0x18;
+ unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i;
int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) {
+ for(i = 1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index fb0c62b18e..877cb5b03b 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -24,13 +24,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id,"COREBOOT",8);
memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
+ header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
- // 3=Workstation,4=Enterprise Server, 7=Performance Server
- fadt->preferred_pm_profile=0x04;
- fadt->sci_int=9;
+ // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+ fadt->preferred_pm_profile = 0x04;
+ fadt->sci_int = 9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
@@ -59,8 +59,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
- fadt->flush_size = 0; // ignored if wbindv=1 in flags
- fadt->flush_stride = 0; // ignored if wbindv=1 in flags
+ fadt->flush_size = 0; // ignored if wbindv = 1 in flags
+ fadt->flush_stride = 0; // ignored if wbindv = 1 in flags
fadt->duty_offset = 1;
fadt->duty_width = 3; // 0 means duty cycle not supported
// _alrm value 0 means RTC alarm feature not supported
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index 9c35814f03..da02095855 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -52,7 +52,7 @@ void get_bus_conf(void)
device_t dev;
int i;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -60,7 +60,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) {
+ for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index 4988ea1691..597acca7e6 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info++;
slot_num++;
//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
pirq_info++;
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 8b5b428f31..ea0b60c525 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -28,12 +28,12 @@ static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
/* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset high. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
@@ -53,11 +53,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
- i=2;
+ /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+ i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret!=0) && (i-->0));
+ } while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
@@ -65,11 +65,11 @@ static inline void change_i2c_mux(unsigned device)
{
int ret, i;
printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
- i=2;
+ i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
- } while ((ret!=0) && (i-->0));
+ } while ((ret != 0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
}
@@ -91,8 +91,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
+#define RC0 ((1 << 1)<<8)
+#define RC1 ((1 << 2)<<8)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Read FIDVID_STATUS */
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
@@ -173,10 +173,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
int i;
- for(i=0;i<2;i++) {
+ for(i = 0; i < 2; i++) {
activate_spd_rom(&sysinfo->ctrl[i]);
}
- for(i=RC0;i<=RC1;i<<=1) {
+ for(i = RC0; i <= RC1; i<<=1) {
change_i2c_mux(i);
}
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c
index 87f065d59c..d69e224cd8 100644
--- a/src/mainboard/hp/dl145_g3/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c
@@ -68,7 +68,7 @@ void get_bus_conf(void)
int i;
struct mb_sysconf_t *m;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -78,7 +78,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) {
+ for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@@ -125,6 +125,6 @@ void get_bus_conf(void)
apicid_base = get_apicid_base(3);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- for(i=0;i<3;i++)
+ for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i;
}
diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c
index 3e256b77e5..6ec1fd8e79 100644
--- a/src/mainboard/hp/dl145_g3/irq_tables.c
+++ b/src/mainboard/hp/dl145_g3/irq_tables.c
@@ -5,45 +5,45 @@
#endif
static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x0, /* Where the interrupt router lies (bus) */
- (0x2<<3)|0x4,
- 0, /* IRQs devoted exclusively to PCI usage */
- 0, /* Vendor */
- 0, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x2a, /* u8 checksum. This has to be set to some
- value that would give 0 after the sum of all
- bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- {0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
- {0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
- {0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
- {0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
- {0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
- {0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
- //{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
- {0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
- {0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
- {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- //{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
- {0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
- }
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x0, /* Where the interrupt router lies (bus) */
+ (0x2 << 3)|0x4,
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0, /* Vendor */
+ 0, /* Device */
+ 0, /* Miniport data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x2a, /* u8 checksum. This has to be set to some
+ value that would give 0 after the sum of all
+ bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
+ {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
+ {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
+ {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
+ {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
+ {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
+ {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
+ //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
+ {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
+ {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
+ {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+ {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
+ {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
+ //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
+ {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
+ }
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 5aeb71dd33..3a784e7828 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
+ * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com>
*
* Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
device_t dev = 0;
int i;
struct resource *res;
- for(i=0; i<3; i++) {
+ for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
+ dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword);
}
// set GEVENT pins to NO OP
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<26);
+ dword |= (1 << 26);
pci_write_config32(dev, 0x64, dword);
}
}
@@ -116,32 +116,32 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//SATA
-/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
-/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
- printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
+/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
+ printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
//USB
printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa);
//VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7);
//PCIE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe);
//IDE
// outb(0x02, 0xc00); outb(0x0e, 0xc01);
// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
-// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
+// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe);
//onboard Broadcom GbE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4);
@@ -153,7 +153,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
- dword |= (1<<4); // enable interrupts
+ dword |= (1 << 4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 12d18cf27d..1d1195a82c 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -79,11 +79,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void setup_early_ipmi_serial()
{
unsigned char result;
- char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
- char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
- char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
- char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
- char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
+ char channel_access[]={0x06 << 2,0x40,0x04,0x80,0x05};
+ char serialmodem_conf[]={0x0c << 2,0x10,0x04,0x08,0x00,0x0f};
+ char serial_mux1[]={0x0c << 2,0x12,0x04,0x06};
+ char serial_mux2[]={0x0c << 2,0x12,0x04,0x03};
+ char serial_mux3[]={0x0c << 2,0x12,0x04,0x07};
// earlydbg(0x0d);
//set channel access system only
@@ -91,19 +91,19 @@ static void setup_early_ipmi_serial()
// earlydbg(result);
/*
//Set serial/modem config
- result=ipmi_request(6,serialmodem_conf);
+ result = ipmi_request(6,serialmodem_conf);
earlydbg(result);
//Set serial mux 1
- result=ipmi_request(4,serial_mux1);
+ result = ipmi_request(4,serial_mux1);
earlydbg(result);
//Set serial mux 2
- result=ipmi_request(4,serial_mux2);
+ result = ipmi_request(4,serial_mux2);
earlydbg(result);
//Set serial mux 3
- result=ipmi_request(4,serial_mux3);
+ result = ipmi_request(4,serial_mux3);
earlydbg(result);
*/
// earlydbg(0x0e);
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
}
#endif
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index e32387386b..68c38813dc 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -69,7 +69,7 @@ void get_bus_conf(void)
int i;
struct mb_sysconf_t *m;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -80,7 +80,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) {
+ for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@@ -124,6 +124,6 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
apicid_base = 0x10;
- for(i=0;i<3;i++)
+ for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i;
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 395de572c1..17e42e4f44 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
+ * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com>
*
* Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
device_t dev = 0;
int i;
struct resource *res;
- for(i=0; i<3; i++) {
+ for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
+ dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword);
}
// set GEVENT pins to NO OP
@@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<26);
+ dword |= (1 << 26);
pci_write_config32(dev, 0x64, dword);
}
}
@@ -113,16 +113,16 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
/* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe << 2)|0, m->apicid_bcm5785[0], 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3 << 2)|0, m->apicid_bcm5785[0], 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|0, m->apicid_bcm5785[2], 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|1, m->apicid_bcm5785[2], 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0 << 2)|0, m->apicid_bcm5785[2], 0xa);
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
@@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
- dword |= (1<<4); // enable interrupts
+ dword |= (1 << 4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 84e28f7fc9..39cd0e339d 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 14:16:19 +0000