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-rw-r--r--src/mainboard/hp/e_vectra_p2706t/Kconfig2
-rw-r--r--src/mainboard/hp/e_vectra_p2706t/devicetree.cb2
-rw-r--r--src/mainboard/hp/e_vectra_p2706t/romstage.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig
index 676d3eb5d8..755b3ac904 100644
--- a/src/mainboard/hp/e_vectra_p2706t/Kconfig
+++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig
@@ -26,7 +26,7 @@ config BOARD_HP_E_VECTRA_P2706T
select ARCH_X86
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
- select SOUTHBRIDGE_INTEL_I82801XX
+ select SOUTHBRIDGE_INTEL_I82801AX
select SUPERIO_NSC_PC87360
select ROMCC
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
index 82209d4317..7ea1f299e7 100644
--- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
+++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb
@@ -8,7 +8,7 @@ chip northbridge/intel/i82810 # Northbridge
device pci_domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 on end # Onboard VGA
- chip southbridge/intel/i82801xx # Southbridge
+ chip southbridge/intel/i82801ax # Southbridge
register "ide0_enable" = "1"
register "ide1_enable" = "1"
diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c
index 50d8c447b4..f2c643c854 100644
--- a/src/mainboard/hp/e_vectra_p2706t/romstage.c
+++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c
@@ -37,7 +37,7 @@
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
#include "pc80/udelay_io.c"
#include "lib/debug.c"
#include "northbridge/intel/i82810/raminit.c"