diff options
Diffstat (limited to 'src/mainboard/hp/dl165_g6_fam10/romstage.c')
-rw-r--r-- | src/mainboard/hp/dl165_g6_fam10/romstage.c | 240 |
1 files changed, 0 insertions, 240 deletions
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c deleted file mode 100644 index 1b91e97ec7..0000000000 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Tyan - * Copyright (C) 2006 AMD - * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. - * - * Copyright (C) 2007 University of Mannheim - * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include "option_table.h" -#include <console/console.h> -#include <timestamp.h> -#include <cpu/amd/model_10xxx_rev.h> -#include <spd.h> -#include <delay.h> -#include <superio/serverengines/pilot/pilot.h> -#include <superio/nsc/pc87417/pc87417.h> -#include <cpu/x86/bist.h> -#include <cpu/amd/car.h> -#include <cpu/amd/msr.h> -#include <northbridge/amd/amdfam10/raminit.h> -#include <northbridge/amd/amdht/ht_wrapper.h> -#include <cpu/amd/family_10h-family_15h/init_cpus.h> -#include <arch/early_variables.h> -#include <cbmem.h> -#include <southbridge/amd/common/reset.h> -#include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "southbridge/broadcom/bcm5785/early_setup.c" - -#include "cpu/amd/quadcore/quadcore.c" - -#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) - -int spd_read_byte(unsigned int device, unsigned int address); - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - u8 val; - outb(0x3d, 0x0cd6); - outb(0x87, 0x0cd7); - - outb(0x44, 0xcd6); - val = inb(0xcd7); - outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); -} - -inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -static const u8 spd_addr[] = { - // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr - //first node - RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#endif -}; - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - struct sys_info *sysinfo = get_sysinfo(); - u32 bsp_apicid = 0, val; - msr_t msr; - - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - bcm5785_enable_lpc(); - pc87417_enable_dev(RTC_DEV); /* Enable RTC */ - } - - post_code(0x30); - - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - - pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - - post_code(0x33); - - cpuSetAMDMSR(0); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ - - wait_all_core0_started(); - -#if CONFIG(LOGICAL_CPUS) - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(bsp_apicid); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif - -#if CONFIG(SET_FIDVID) - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); - - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - post_code(0x39); - - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr = rdmsr(MSR_COFVID_STS); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -#endif - - init_timer(); - - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset - shouldn't see this message!!!\n"); - } - - /* It's the time to set ctrl in sysinfo now; */ - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); - - //do we need ACPI timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID - - timestamp_add_now(TS_BEFORE_INITRAM); - printk(BIOS_DEBUG, "raminit_amdmct()\n"); - raminit_amdmct(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); - - cbmem_initialize_empty(); - post_code(0x41); - - amdmct_cbmem_store_info(sysinfo); - - bcm5785_early_setup(); -} - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] node = The node on which this chain is located - * @param[in] link = The link on the host for this chain - * @param[out] List = supply a pointer to a list - */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} |