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-rw-r--r--src/mainboard/hp/2760p/devicetree.cb1
-rw-r--r--src/mainboard/hp/2760p/romstage.c2
2 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb
index 515d20f761..a301857b7a 100644
--- a/src/mainboard/hp/2760p/devicetree.cb
+++ b/src/mainboard/hp/2760p/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
+ # mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index 68af61ba22..ba6f9566cf 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -27,8 +27,6 @@ void pch_enable_lpc(void)
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
}
void mainboard_rcba_config(void)