diff options
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/overridetree.cb | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 76b9dcd82a..1b37784bcd 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -36,9 +36,6 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" - # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) - register "tcc_offset" = "20" - # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index c43c09f0fb..1cc0530db8 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -64,9 +64,6 @@ chip soc/intel/meteorlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - # Temporary setting TCC of 90C = Tj max - Tcc - register "tcc_offset" = "20" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |