diff options
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/myst/port_descriptors.c | 4 | ||||
-rw-r--r-- | src/mainboard/google/myst/variants/baseboard/gpio.c | 14 |
2 files changed, 14 insertions, 4 deletions
diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 108dd4e639..6d0d0d6ff9 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -54,8 +54,6 @@ static const fsp_dxio_descriptor emmc_descriptor = { .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, - /* TODO(b/284213391): Fix PCIe shutdown */ - .link_hotplug = 3, .clk_req = CLK_REQ3, }; @@ -68,8 +66,6 @@ static const fsp_dxio_descriptor nvme_descriptor = { .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, - /* TODO(b/284213391): Fix PCIe shutdown */ - .link_hotplug = 3, .clk_req = CLK_REQ3, }; diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index efd654e652..f97cc16459 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -196,8 +196,22 @@ static const struct soc_amd_gpio early_gpio_table[] = { /* PCIE_RST needs to be brought high before FSP-M runs */ static const struct soc_amd_gpio romstage_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ + /* SD_AUX_RST */ + PAD_GPO(GPIO_29, LOW), + /* SSD_AUX_RESET */ + PAD_GPO(GPIO_31, LOW), /* WLAN_AUX_RST_L (ACTIVE LOW) */ PAD_GPO(GPIO_38, HIGH), + /* WWAN_AUX_RST_L (ACTIVE LOW) */ + PAD_GPO(GPIO_39, HIGH), + /* CLK_REQ0_L / WLAN */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* CLK_REQ1_L / SD */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L / WWAN */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* CLK_REQ3_L / SSD */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), }; |