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-rw-r--r--src/mainboard/google/butterfly/devicetree.cb22
-rw-r--r--src/mainboard/google/butterfly/early_init.c46
-rw-r--r--src/mainboard/google/link/devicetree.cb21
-rw-r--r--src/mainboard/google/link/early_init.c42
-rw-r--r--src/mainboard/google/parrot/devicetree.cb20
-rw-r--r--src/mainboard/google/parrot/early_init.c45
-rw-r--r--src/mainboard/google/stout/devicetree.cb25
-rw-r--r--src/mainboard/google/stout/early_init.c50
8 files changed, 101 insertions, 170 deletions
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 5b3841a1f0..a72d984369 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -18,7 +18,27 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x000001e8"
register "gpu_pch_backlight" = "0x03d00000"
- register "max_mem_clock_mhz" = "666" # DDR3-1333
+ register "ec_present" = "1"
+ # FIXME: Native raminit requires reduced max clock
+ register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+ # Force double refresh rate
+ register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE"
+
+ register "usb_port_config" = "{
+ { 1, 0, 0x0040 },
+ { 1, 0, 0x0040 },
+ { 1, 0, 0x0040 },
+ { 0, 0, 0x0000 },
+ { 0, 0, 0x0000 },
+ { 0, 0, 0x0000 },
+ { 0, 0, 0x0000 },
+ { 0, 0, 0x0000 },
+ { 0, 4, 0x0000 },
+ { 1, 4, 0x0080 },
+ { 1, 4, 0x0040 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },}"
device domain 0 on
device ref host_bridge on end # host bridge
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index 4e9639fd94..e658d37465 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -74,45 +74,9 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data_template = {
- .pei_version = PEI_VERSION,
- .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
- .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
- .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
- .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
- .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_BASE_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
- .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
- .ec_present = 1,
- .ddr3lv_support = 0,
- .max_ddr3_freq = 1600,
- .usb_port_config = {
- /* enabled USB oc pin length */
- { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
- { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
- { 1, 0, 0x0040 }, /* P2: Camera (no OC) */
- { 0, 0, 0x0000 }, /* P3: Empty */
- { 0, 0, 0x0000 }, /* P4: Empty */
- { 0, 0, 0x0000 }, /* P5: Empty */
- { 0, 0, 0x0000 }, /* P6: Empty */
- { 0, 0, 0x0000 }, /* P7: Empty */
- { 0, 4, 0x0000 }, /* P8: Empty */
- { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
- { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
- { 0, 4, 0x0000 }, /* P11: Empty */
- { 0, 4, 0x0000 }, /* P12: Empty */
- { 0, 4, 0x0000 }, /* P13: Empty */
- },
- .ddr_refresh_rate_config = 2, /* Force double refresh rate */
- };
- *pei_data = pei_data_template;
+ const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+ memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
}
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index c5a0a08455..88983dcfc6 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -17,7 +17,26 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
- register "max_mem_clock_mhz" = "666"
+ register "ec_present" = "1"
+ register "ddr3lv_support" = "1"
+ # FIXME: Native raminit requires reduced max clock
+ register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+ register "usb_port_config" = "{
+ { 0, 3, 0x0000 },
+ { 1, 0, 0x0040 },
+ { 1, 1, 0x0040 },
+ { 1, 3, 0x0040 },
+ { 0, 3, 0x0000 },
+ { 1, 3, 0x0040 },
+ { 0, 3, 0x0000 },
+ { 0, 3, 0x0000 },
+ { 1, 4, 0x0040 },
+ { 1, 4, 0x0040 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },}"
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 17e8b54b96..a4127f14d8 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -83,46 +83,8 @@ static uint8_t *locate_spd(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data_template = {
- .pei_version = PEI_VERSION,
- .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
- .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
- .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
- .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
- .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_BASE_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
- .ec_present = 1,
- .ddr3lv_support = 1,
- .max_ddr3_freq = 1600,
- .usb_port_config = {
- /* Empty and onboard Ports 0-7, set to un-used pin OC3 */
- { 0, 3, 0x0000 }, /* P0: Empty */
- { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
- { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
- { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */
- { 0, 3, 0x0000 }, /* P4: Empty */
- { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */
- { 0, 3, 0x0000 }, /* P6: Empty */
- { 0, 3, 0x0000 }, /* P7: Empty */
- /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
- { 1, 4, 0x0040 }, /* P8: Camera (no OC) */
- { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */
- { 0, 4, 0x0000 }, /* P10: Empty */
- { 0, 4, 0x0000 }, /* P11: Empty */
- { 0, 4, 0x0000 }, /* P12: Empty */
- { 0, 4, 0x0000 }, /* P13: Empty */
- },
- };
- *pei_data = pei_data_template;
+ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
+
/* LINK has 2 channels of memory down, so spd_data[0] and [2]
both need to be populated */
memcpy(pei_data->spd_data[0], locate_spd(),
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 6bc4b454d6..bf1bff36f2 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -17,7 +17,25 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x000001d4"
register "gpu_pch_backlight" = "0x03aa0000"
- register "max_mem_clock_mhz" = "666"
+ register "ec_present" = "1"
+ # FIXME: Native raminit requires reduced max clock
+ register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+ register "usb_port_config" = "{
+ { 0, 3, 0x0000 },
+ { 1, 0, 0x0040 },
+ { 1, 1, 0x0040 },
+ { 1, 1, 0x0040 },
+ { 0, 3, 0x0000 },
+ { 0, 3, 0x0000 },
+ { 0, 3, 0x0000 },
+ { 0, 3, 0x0000 },
+ { 1, 4, 0x0040 },
+ { 0, 4, 0x0000 },
+ { 1, 4, 0x0040 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },
+ { 0, 4, 0x0000 },}"
device domain 0 on
device ref host_bridge on end # host bridge
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index ba93531cb5..efdb9a2fea 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -52,46 +52,11 @@ void mainboard_late_rcba_config(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data_template = {
- .pei_version = PEI_VERSION,
- .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
- .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
- .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
- .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
- .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_BASE_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
- .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
- .ec_present = 1,
- .max_ddr3_freq = 1600,
- .usb_port_config = {
- /* Empty and onboard Ports 0-7, set to un-used pin OC3 */
- { 0, 3, 0x0000 }, /* P0: Empty */
- { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
- { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
- { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */
- { 0, 3, 0x0000 }, /* P4: Empty */
- { 0, 3, 0x0000 }, /* P5: Empty */
- { 0, 3, 0x0000 }, /* P6: Empty */
- { 0, 3, 0x0000 }, /* P7: Empty */
- /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
- { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
- { 0, 4, 0x0000 }, /* P9: Empty */
- { 1, 4, 0x0040 }, /* P10: Camera (no OC) */
- { 0, 4, 0x0000 }, /* P11: Empty */
- { 0, 4, 0x0000 }, /* P12: Empty */
- { 0, 4, 0x0000 }, /* P13: Empty */
- },
- };
- *pei_data = pei_data_template;
+ const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+ memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 6710b41ac6..a2b8452d99 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -17,7 +17,30 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
- register "max_mem_clock_mhz" = "666"
+ register "ec_present" = "1"
+ # FIXME: Native raminit requires reduced max clock
+ register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+ register "usb_port_config" = "{
+ { 1, 0, 0x0040 },
+ { 1, 0, 0x0040 },
+ { 0, 1, 0x0000 },
+ { 1, 1, 0x0040 },
+ { 1, 1, 0x0040 },
+ { 1, 1, 0x0040 },
+ { 0, 1, 0x0000 },
+ { 0, 1, 0x0000 },
+ { 0, 5, 0x0000 },
+ { 1, 4, 0x0040 },
+ { 0, 5, 0x0000 },
+ { 0, 5, 0x0000 },
+ { 0, 5, 0x0000 },
+ { 1, 5, 0x0040 },}"
+
+ register "usb3.mode" = "2" # Auto
+ register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1
+ register "usb3.preboot_support" = "0" # No PreOS boot support
+ register "usb3.xhci_streams" = "1" # Sure, lets have streams
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index e5ed8e91ac..85c4e154dd 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -89,51 +89,11 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data_template = {
- .pei_version = PEI_VERSION,
- .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
- .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
- .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
- .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
- .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_BASE_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
- .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
- .ec_present = 1,
- .max_ddr3_freq = 1600,
- .usb_port_config = {
- /* enabled USB oc pin length */
- { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */
- { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */
- { 0, 1, 0x0000 }, /* P2: Empty */
- { 1, 1, 0x0040 }, /* P3: Camera (no OC) */
- { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */
- { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */
- { 0, 1, 0x0000 }, /* P6: Empty */
- { 0, 1, 0x0000 }, /* P7: Empty */
- { 0, 5, 0x0000 }, /* P8: Empty */
- { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */
- { 0, 5, 0x0000 }, /* P10: Empty */
- { 0, 5, 0x0000 }, /* P11: Empty */
- { 0, 5, 0x0000 }, /* P12: Empty */
- { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */
- },
- .usb3 = {
- .mode = XHCI_MODE,
- .hs_port_switch_mask = XHCI_PORTS,
- .preboot_support = XHCI_PREBOOT,
- .xhci_streams = XHCI_STREAMS,
- },
- };
- *pei_data = pei_data_template;
+ const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+ memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+ /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
}
void mainboard_early_init(int s3resume)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 16:20:12 +0000