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-rw-r--r--src/mainboard/google/samus/Kconfig14
-rw-r--r--src/mainboard/google/samus/Makefile.inc4
-rw-r--r--src/mainboard/google/samus/acpi/chromeos.asl6
-rw-r--r--src/mainboard/google/samus/acpi/mainboard.asl24
-rw-r--r--src/mainboard/google/samus/acpi/platform.asl14
-rw-r--r--src/mainboard/google/samus/acpi/thermal.asl14
-rw-r--r--src/mainboard/google/samus/acpi_tables.c64
-rw-r--r--src/mainboard/google/samus/chromeos.c14
-rw-r--r--src/mainboard/google/samus/devicetree.cb161
-rw-r--r--src/mainboard/google/samus/dsdt.asl14
-rw-r--r--src/mainboard/google/samus/fadt.c113
-rw-r--r--src/mainboard/google/samus/gpio.h198
-rw-r--r--src/mainboard/google/samus/mainboard.c7
-rw-r--r--src/mainboard/google/samus/pei_data.c81
-rw-r--r--src/mainboard/google/samus/romstage.c161
-rw-r--r--src/mainboard/google/samus/smihandler.c43
-rw-r--r--src/mainboard/google/samus/spd.c121
-rw-r--r--src/mainboard/google/samus/spd.h43
-rw-r--r--src/mainboard/google/samus/thermal.h3
19 files changed, 491 insertions, 608 deletions
diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig
index cbfe2f2a4f..7769d24c79 100644
--- a/src/mainboard/google/samus/Kconfig
+++ b/src/mainboard/google/samus/Kconfig
@@ -2,10 +2,7 @@ if BOARD_GOOGLE_SAMUS
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select CPU_INTEL_SOCKET_RPGA989
- select NORTHBRIDGE_INTEL_HASWELL
- select SOUTHBRIDGE_INTEL_LYNXPOINT
- select INTEL_LYNXPOINT_LP
+ select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
select EC_SOFTWARE_SYNC
@@ -18,13 +15,17 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
- select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select CHROMEOS_RAMOOPS_DYNAMIC
select INTEL_INT15
config VBOOT_RAMSTAGE_INDEX
hex
default 0x2
+config VBOOT_REFCODE_INDEX
+ hex
+ default 0x3
+
config MAINBOARD_DIR
string
default google/samus
@@ -33,9 +34,6 @@ config MAINBOARD_PART_NUMBER
string
default "Samus"
-config MMCONF_BASE_ADDRESS
- hex
- default 0xf0000000
config MAX_CPUS
int
diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc
index 343bdf4dc6..f23352f471 100644
--- a/src/mainboard/google/samus/Makefile.inc
+++ b/src/mainboard/google/samus/Makefile.inc
@@ -24,7 +24,11 @@ ramstage-y += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += pei_data.c
+ramstage-y += pei_data.c
+
## DIMM SPD for on-board memory
+romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# Order of names in SPD_SOURCES is important!
diff --git a/src/mainboard/google/samus/acpi/chromeos.asl b/src/mainboard/google/samus/acpi/chromeos.asl
index 5baa1a36e7..132f65df23 100644
--- a/src/mainboard/google/samus/acpi/chromeos.asl
+++ b/src/mainboard/google/samus/acpi/chromeos.asl
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
- Package () { 0x0003, 1, 16, "LynxPoint" }, // firmware write protect
+Name (OIPG, Package() {
+ Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
+ Package () { 0x0003, 1, 16, "PCH-LP" }, // firmware write protect
})
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl
index f0b19961cb..72bff6ce3e 100644
--- a/src/mainboard/google/samus/acpi/mainboard.asl
+++ b/src/mainboard/google/samus/acpi/mainboard.asl
@@ -65,16 +65,6 @@ Scope (\_SB)
})
Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
-
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GWAK (Local0)
- }
- }
}
Device (TSCR)
@@ -98,19 +88,5 @@ Scope (\_SB)
BOARD_TOUCHSCREEN_I2C_ADDR
}
})
-
-#if 0 // Disabled until kernel driver is working
- Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
-
- Method (_DSW, 3, NotSerialized)
- {
- Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
-
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- \_SB.PCI0.LPCB.GWAK (Local0)
- }
- }
-#endif
}
}
diff --git a/src/mainboard/google/samus/acpi/platform.asl b/src/mainboard/google/samus/acpi/platform.asl
index 208d76a0e9..e6aaf75952 100644
--- a/src/mainboard/google/samus/acpi/platform.asl
+++ b/src/mainboard/google/samus/acpi/platform.asl
@@ -68,19 +68,5 @@ Method(_PTS,1)
Method(_WAK,1)
{
- /* Update AC status */
- Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
- if (LNotEqual (Local0, \PWRS)) {
- Store (Local0, \PWRS)
- Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
- }
-
- /* Update LID status */
- Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
- if (LNotEqual (Local0, \LIDS)) {
- Store (Local0, \LIDS)
- Notify (\_SB.LID0, 0x80)
- }
-
Return(Package(){0,0})
}
diff --git a/src/mainboard/google/samus/acpi/thermal.asl b/src/mainboard/google/samus/acpi/thermal.asl
index a622d6cba6..2bd18091fd 100644
--- a/src/mainboard/google/samus/acpi/thermal.asl
+++ b/src/mainboard/google/samus/acpi/thermal.asl
@@ -21,20 +21,6 @@
Scope (\_TZ)
{
- // Handler for throttle requests on this platform
- // 0 = Stop throttling
- // 1 = Start throttling
- Method (THRT, 1, Serialized)
- {
- If (LEqual (Arg0, 0)) {
- /* Disable Power Limit */
- \_SB.PCI0.MCHC.CTLD ()
- } Else {
- /* Enable Power Limit */
- \_SB.PCI0.MCHC.CTLE (\F0PW)
- }
- }
-
ThermalZone (THRM)
{
Name (_TC1, 0x02)
diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c
index 1978494014..738bb3b369 100644
--- a/src/mainboard/google/samus/acpi_tables.c
+++ b/src/mainboard/google/samus/acpi_tables.c
@@ -29,51 +29,27 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
+#include <broadwell/acpi.h>
+#include <broadwell/nvs.h>
#include "thermal.h"
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
- gnvs->tmps = TEMPERATURE_SENSOR_ID;
- gnvs->tcrt = CRITICAL_TEMPERATURE;
- gnvs->tpsv = PASSIVE_TEMPERATURE;
- gnvs->tmax = MAX_TEMPERATURE;
- gnvs->f0pw = EC_THROTTLE_POWER_LIMIT;
- gnvs->flvl = 1;
-}
-
void acpi_create_gnvs(global_nvs_t *gnvs)
{
+ acpi_init_gnvs(gnvs);
+
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
- gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
- gnvs->s5u1 = 0;
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
-#if CONFIG_CHROMEOS
- gnvs->chromeos.vbt2 = google_ec_running_ro() ?
- ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
-
- acpi_update_thermal_table(gnvs);
+ gnvs->tmps = TEMPERATURE_SENSOR_ID;
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
}
unsigned long acpi_fill_madt(unsigned long current)
@@ -85,27 +61,5 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- /* GPIO Controller */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 14, 14, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- // Not implemented
- return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- /* No NUMA, no SRAT */
- return current;
+ return acpi_madt_irq_overrides(current);
}
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
index 092833c5c5..8e6e57229d 100644
--- a/src/mainboard/google/samus/chromeos.c
+++ b/src/mainboard/google/samus/chromeos.c
@@ -22,12 +22,12 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-#if CONFIG_EC_GOOGLE_CHROMEEC
-#include "ec.h"
+#include <console/console.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include <ec/google/chromeec/ec.h>
-#endif
+#include <ec/google/chromeec/ec_commands.h>
+#include <broadwell/gpio.h>
+
/* SPI Write protect is GPIO 16 */
#define CROS_WP_GPIO 16
@@ -39,13 +39,9 @@
static int get_lid_switch(void)
{
-#if CONFIG_EC_GOOGLE_CHROMEEC
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
return !!(ec_switches & EC_SWITCH_LID_OPEN);
-#else
- return 0;
-#endif
}
void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index 12a21ecdb0..3e87eca103 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -1,4 +1,4 @@
-chip northbridge/intel/haswell
+chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
@@ -21,104 +21,81 @@ chip northbridge/intel/haswell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- device cpu_cluster 0 on
- chip cpu/intel/socket_rPGA989
- device lapic 0 on end
- end
- chip cpu/intel/haswell
- # Magic APIC ID to locate this chip
- device lapic 0xACAC off end
-
- register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S)
- register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10)
-
- register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
- register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S)
- register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10)
- end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
- chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
+ # EC range is 0x800-0x9ff
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
+ # EC_SMI is GPIO34
+ register "alt_gp_smi_en" = "0x0004"
+ register "gpe0_en_1" = "0x00000000"
+ # EC_SCI is GPIO36
+ register "gpe0_en_2" = "0x00000010"
+ register "gpe0_en_3" = "0x00000000"
+ register "gpe0_en_4" = "0x00000000"
- # EC_SMI is GPIO34
- register "alt_gp_smi_en" = "0x0004"
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
+ register "sata_port_map" = "0x1"
+ register "sio_acpi_mode" = "0"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
- register "sata_port_map" = "0x1"
+ # Force enable ASPM for PCIe Port 1
+ register "pcie_port_force_aspm" = "0x01"
- register "sio_acpi_mode" = "0"
- register "sio_i2c0_voltage" = "0" # 3.3V
- register "sio_i2c1_voltage" = "0" # 3.3V
+ # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+ register "icc_clock_disable" = "0x013e0000"
- # Force enable ASPM for PCIe Port 1
- register "pcie_port_force_aspm" = "0x01"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
- # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013e0000"
-
- # Route all USB ports to XHCI per default
- register "xhci_default" = "1"
-
- device pci 13.0 on end # Smart Sound Audio DSP
- device pci 14.0 on end # USB3 XHCI
- device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
- device pci 15.3 off end # GSPI0
- device pci 15.4 off end # GSPI1
- device pci 15.5 off end # UART0
- device pci 15.6 off end # UART1
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT
- device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
- device pci 1b.0 off end # High Definition Audio
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 off end # PCIe Port #3
- device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1d.0 on end # USB2 EHCI
- device pci 1e.0 off end # PCI bridge
- device pci 1f.0 on
- chip ec/google/chromeec
- # We only have one init function that
- # we need to call to initialize the
- # keyboard part of the EC.
- device pnp ff.1 on # dummy address
- end
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+ device pci 03.0 on end # mini-hd audio
+ device pci 13.0 on end # Smart Sound Audio DSP
+ device pci 14.0 on end # USB3 XHCI
+ device pci 15.0 on end # Serial I/O DMA
+ device pci 15.1 on end # I2C0
+ device pci 15.2 on end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 off end # GbE
+ device pci 1b.0 off end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 off end # USB2 EHCI
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
end
- end # LPC bridge
- device pci 1f.2 on end # SATA Controller
- device pci 1f.3 off end # SMBus
- device pci 1f.6 on end # Thermal
- end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller
+ device pci 1f.3 off end # SMBus
+ device pci 1f.6 on end # Thermal
end
end
diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl
index 343279c086..ea0d01b176 100644
--- a/src/mainboard/google/samus/dsdt.asl
+++ b/src/mainboard/google/samus/dsdt.asl
@@ -31,22 +31,21 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
// global NVS and variables
- #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <soc/intel/broadwell/acpi/globalnvs.asl>
// General Purpose Events
//#include "acpi/gpe.asl"
// CPU
- #include <cpu/intel/haswell/acpi/cpu.asl>
+ #include <soc/intel/broadwell/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
- #include <northbridge/intel/haswell/acpi/haswell.asl>
- #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ #include <soc/intel/broadwell/acpi/systemagent.asl>
+ #include <soc/intel/broadwell/acpi/pch.asl>
}
}
@@ -58,5 +57,8 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
// Chipset specific sleep states
- #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+ #include <soc/intel/broadwell/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
}
diff --git a/src/mainboard/google/samus/fadt.c b/src/mainboard/google/samus/fadt.c
index 7afbbfa698..bcc08fd8eb 100644
--- a/src/mainboard/google/samus/fadt.c
+++ b/src/mainboard/google/samus/fadt.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,20 +19,16 @@
*/
#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/pch.h>
+#include <broadwell/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
- u16 pmbase = get_pmbase();
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
- header->revision = 3;
+ header->revision = 5;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
@@ -42,114 +39,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0;
-
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x80;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 32;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 87;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
-
- fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 0;
- fadt->x_gpe0_blk.bit_width = 0;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = 0;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
+ acpi_fill_in_fadt(fadt);
header->checksum =
acpi_checksum((void *) fadt, header->length);
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h
index bc4d2f35e8..c98be4d7e3 100644
--- a/src/mainboard/google/samus/gpio.h
+++ b/src/mainboard/google/samus/gpio.h
@@ -20,105 +20,107 @@
#ifndef SAMUS_GPIO_H
#define SAMUS_GPIO_H
-struct pch_lp_gpio_map;
+#include <broadwell/gpio.h>
-const struct pch_lp_gpio_map mainboard_gpio_map[] = {
- LP_GPIO_UNUSED, /* 0: UNUSED */
- LP_GPIO_UNUSED, /* 1: UNUSED */
- LP_GPIO_UNUSED, /* 2: UNUSED */
- LP_GPIO_UNUSED, /* 3: UNUSED */
- LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
- LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
- LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
- LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
- LP_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
- LP_GPIO_IRQ_EDGE, /* 9: NFC_INT (GPIO IRQ) */
- LP_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
- LP_GPIO_UNUSED, /* 11: UNUSED */
- LP_GPIO_UNUSED, /* 12: UNUSED */
- LP_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */
- LP_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */
- LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
- LP_GPIO_INPUT, /* 16: PCH_WP */
- LP_GPIO_UNUSED, /* 17: UNUSED */
- LP_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */
- LP_GPIO_UNUSED, /* 19: UNUSED */
- LP_GPIO_UNUSED, /* 20: UNUSED */
- LP_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */
- LP_GPIO_UNUSED, /* 22: UNUSED */
- LP_GPIO_OUT_HIGH, /* 23: PP3300_AUTOBAHN_EN */
- LP_GPIO_UNUSED, /* 24: UNUSED */
- LP_GPIO_INPUT, /* 25: EC_IN_RW */
- LP_GPIO_OUT_HIGH, /* 26: NFC_EN */
- LP_GPIO_UNUSED, /* 27: UNUSED */
- LP_GPIO_UNUSED, /* 28: UNUSED */
- LP_GPIO_UNUSED, /* 29: UNUSED */
- LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
- LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
- LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
- LP_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */
- LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
- LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
- LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
- LP_GPIO_UNUSED, /* 37: UNUSED */
- LP_GPIO_UNUSED, /* 38: UNUSED */
- LP_GPIO_UNUSED, /* 39: UNUSED */
- LP_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */
- LP_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
- LP_GPIO_OUT_HIGH, /* 42: WLAN_DISABLE_L */
- LP_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */
- LP_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */
- LP_GPIO_PIRQ, /* 45: ACCEL_INT (PIRQW) */
- LP_GPIO_PIRQ, /* 46: CODEC_INT_L (PIRQO) */
- LP_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */
- LP_GPIO_UNUSED, /* 48: UNUSED */
- LP_GPIO_INPUT, /* 49: HDMI_CEC */
- LP_GPIO_UNUSED, /* 50: UNUSED */
- LP_GPIO_UNUSED, /* 51: UNUSED */
- LP_GPIO_INPUT, /* 52: SIM_DET */
- LP_GPIO_UNUSED, /* 53: UNUSED */
- LP_GPIO_UNUSED, /* 54: UNUSED */
- LP_GPIO_UNUSED, /* 55: UNUSED */
- LP_GPIO_UNUSED, /* 56: UNUSED */
- LP_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */
- LP_GPIO_UNUSED, /* 58: UNUSED */
- LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
- LP_GPIO_UNUSED, /* 60: UNUSED */
- LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
- LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
- LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
- LP_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */
- LP_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */
- LP_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */
- LP_GPIO_INPUT, /* 67: RAM_ID0 */
- LP_GPIO_INPUT, /* 68: RAM_ID1 */
- LP_GPIO_INPUT, /* 69: RAM_ID2 */
- LP_GPIO_OUT_HIGH, /* 70: LTE_POWER_ON */
- LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
- LP_GPIO_UNUSED, /* 72: UNUSED */
- LP_GPIO_UNUSED, /* 73: UNUSED */
- LP_GPIO_UNUSED, /* 74: UNUSED */
- LP_GPIO_UNUSED, /* 75: UNUSED */
- LP_GPIO_UNUSED, /* 76: UNUSED */
- LP_GPIO_UNUSED, /* 77: UNUSED */
- LP_GPIO_UNUSED, /* 78: UNUSED */
- LP_GPIO_UNUSED, /* 79: UNUSED */
- LP_GPIO_UNUSED, /* 80: UNUSED */
- LP_GPIO_UNUSED, /* 81: UNUSED */
- LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
- LP_GPIO_UNUSED, /* 83: UNUSED */
- LP_GPIO_UNUSED, /* 84: UNUSED */
- LP_GPIO_UNUSED, /* 85: UNUSED */
- LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
- LP_GPIO_UNUSED, /* 87: UNUSED */
- LP_GPIO_UNUSED, /* 88: UNUSED */
- LP_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */
- LP_GPIO_UNUSED, /* 90: UNUSED */
- LP_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */
- LP_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */
- LP_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */
- LP_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */
- LP_GPIO_END
+#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
+
+static const struct gpio_config mainboard_gpio_config[] = {
+ PCH_GPIO_UNUSED, /* 0: UNUSED */
+ PCH_GPIO_UNUSED, /* 1: UNUSED */
+ PCH_GPIO_UNUSED, /* 2: UNUSED */
+ PCH_GPIO_UNUSED, /* 3: UNUSED */
+ PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
+ PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
+ PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
+ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
+ PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */
+ PCH_GPIO_IRQ_EDGE, /* 9: NFC_INT (GPIO IRQ) */
+ PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */
+ PCH_GPIO_UNUSED, /* 11: UNUSED */
+ PCH_GPIO_UNUSED, /* 12: UNUSED */
+ PCH_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */
+ PCH_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */
+ PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
+ PCH_GPIO_INPUT, /* 16: PCH_WP */
+ PCH_GPIO_UNUSED, /* 17: UNUSED */
+ PCH_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */
+ PCH_GPIO_UNUSED, /* 19: UNUSED */
+ PCH_GPIO_UNUSED, /* 20: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */
+ PCH_GPIO_UNUSED, /* 22: UNUSED */
+ PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */
+ PCH_GPIO_UNUSED, /* 24: UNUSED */
+ PCH_GPIO_INPUT, /* 25: EC_IN_RW */
+ PCH_GPIO_OUT_HIGH, /* 26: NFC_EN */
+ PCH_GPIO_UNUSED, /* 27: UNUSED */
+ PCH_GPIO_UNUSED, /* 28: UNUSED */
+ PCH_GPIO_UNUSED, /* 29: UNUSED */
+ PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
+ PCH_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
+ PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
+ PCH_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */
+ PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
+ PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+ PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
+ PCH_GPIO_UNUSED, /* 37: UNUSED */
+ PCH_GPIO_UNUSED, /* 38: UNUSED */
+ PCH_GPIO_UNUSED, /* 39: UNUSED */
+ PCH_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */
+ PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */
+ PCH_GPIO_OUT_HIGH, /* 42: WLAN_DISABLE_L */
+ PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */
+ PCH_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */
+ PCH_GPIO_PIRQ, /* 45: ACCEL_INT (PIRQW) */
+ PCH_GPIO_PIRQ, /* 46: CODEC_INT_L (PIRQO) */
+ PCH_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */
+ PCH_GPIO_UNUSED, /* 48: UNUSED */
+ PCH_GPIO_INPUT, /* 49: HDMI_CEC */
+ PCH_GPIO_UNUSED, /* 50: UNUSED */
+ PCH_GPIO_UNUSED, /* 51: UNUSED */
+ PCH_GPIO_INPUT, /* 52: SIM_DET */
+ PCH_GPIO_UNUSED, /* 53: UNUSED */
+ PCH_GPIO_UNUSED, /* 54: UNUSED */
+ PCH_GPIO_UNUSED, /* 55: UNUSED */
+ PCH_GPIO_UNUSED, /* 56: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */
+ PCH_GPIO_UNUSED, /* 58: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
+ PCH_GPIO_UNUSED, /* 60: UNUSED */
+ PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */
+ PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */
+ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SS5_L */
+ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */
+ PCH_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */
+ PCH_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */
+ PCH_GPIO_INPUT, /* 67: RAM_ID0 */
+ PCH_GPIO_INPUT, /* 68: RAM_ID1 */
+ PCH_GPIO_INPUT, /* 69: RAM_ID2 */
+ PCH_GPIO_OUT_HIGH, /* 70: LTE_POWER_ON */
+ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
+ PCH_GPIO_UNUSED, /* 72: UNUSED */
+ PCH_GPIO_UNUSED, /* 73: UNUSED */
+ PCH_GPIO_UNUSED, /* 74: UNUSED */
+ PCH_GPIO_UNUSED, /* 75: UNUSED */
+ PCH_GPIO_UNUSED, /* 76: UNUSED */
+ PCH_GPIO_UNUSED, /* 77: UNUSED */
+ PCH_GPIO_UNUSED, /* 78: UNUSED */
+ PCH_GPIO_UNUSED, /* 79: UNUSED */
+ PCH_GPIO_UNUSED, /* 80: UNUSED */
+ PCH_GPIO_UNUSED, /* 81: UNUSED */
+ PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
+ PCH_GPIO_UNUSED, /* 83: UNUSED */
+ PCH_GPIO_UNUSED, /* 84: UNUSED */
+ PCH_GPIO_UNUSED, /* 85: UNUSED */
+ PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
+ PCH_GPIO_UNUSED, /* 87: UNUSED */
+ PCH_GPIO_UNUSED, /* 88: UNUSED */
+ PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */
+ PCH_GPIO_UNUSED, /* 90: UNUSED */
+ PCH_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */
+ PCH_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */
+ PCH_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */
+ PCH_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */
+ PCH_GPIO_END
};
#endif
diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c
index 7977ce3af1..fdc7d78769 100644
--- a/src/mainboard/google/samus/mainboard.c
+++ b/src/mainboard/google/samus/mainboard.c
@@ -32,16 +32,9 @@
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
-#include <southbridge/intel/lynxpoint/pch.h>
#include "ec.h"
#include "onboard.h"
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
mainboard_ec_init();
diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c
new file mode 100644
index 0000000000..c4e9c0bb29
--- /dev/null
+++ b/src/mainboard/google/samus/pei_data.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <broadwell/gpio.h>
+#include <broadwell/pei_data.h>
+#include <broadwell/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* DQ byte map for Samus board */
+ const u8 dq_map[2][6][2] = {
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+ /* DQS CPU<>DRAM map for Samus board */
+ const u8 dqs_map[2][8] = {
+ { 2, 0, 1, 3, 6, 4, 7, 5 },
+ { 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+ /* P0: HOST PORT */
+ pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P1: HOST PORT */
+ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+ USB_PORT_BACK_PANEL);
+ /* P2: EMPTY */
+ pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P3: SD CARD */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 0, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P4: EMPTY */
+ pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P5: WWAN */
+ pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P6: CAMERA */
+ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P7: BT */
+ pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+
+ /* P1: HOST PORT */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: HOST PORT */
+ pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+ /* P3: EMPTY */
+ pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+ /* P4: SD CARD */
+ pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index bdf0e7057a..f0609c84a7 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -18,151 +18,40 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
#include <cbfs.h>
#include <console/console.h>
-#include <cpu/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/raminit.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+//#include <broadwell/gpio.h>
+#include <broadwell/pei_data.h>
+#include <broadwell/pei_wrapper.h>
+#include <broadwell/romstage.h>
+#include "spd.h"
#include "gpio.h"
-const struct rcba_config_instruction rcba_config[] = {
-
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP PCIE INTA -> PIRQA
- * D29IP_E1P EHCI INTA -> PIRQD
- * D20IP_XHCI XHCI INTA -> PIRQC (MSI)
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
- RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
- RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP)),
- RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
- RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
- RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
- RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
-
- /* Device interrupt route registers */
- RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
- RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
- RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
- RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
- RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
- RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
- RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
- RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
-
- /* Disable unused devices (board specific) */
- RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
-
- RCBA_END_CONFIG,
-};
-
-/* Copy SPD data for on-board memory */
-static void copy_spd(struct pei_data *peid)
+void mainboard_romstage_entry(struct romstage_params *rp)
{
- const int gpio_vector[] = {67, 68, 69, -1};
- int spd_index = get_gpios(gpio_vector);
- char *spd_file;
- size_t spd_file_len;
+ struct pei_data pei_data;
- printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
- spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
+ post_code(0x32);
- if (spd_file_len <
- ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
- if (spd_file_len < sizeof(peid->spd_data[0]))
- die("Missing SPD data.");
+ /* Initialize GPIOs */
+ init_gpios(mainboard_gpio_config);
- memcpy(peid->spd_data[0],
- spd_file +
- spd_index * sizeof(peid->spd_data[0]),
- sizeof(peid->spd_data[0]));
-}
+ /* Fill out PEI DATA */
+ memset(&pei_data, 0, sizeof(pei_data));
+ mainboard_fill_pei_data(&pei_data);
+ mainboard_fill_spd_data(&pei_data);
+ rp->pei_data = &pei_data;
-void mainboard_romstage_entry(unsigned long bist)
-{
- struct pei_data pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = DEFAULT_MCHBAR,
- .dmibar = DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = DEFAULT_PCIEXBAR,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
- .ec_present = 1,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 2,
- .dimm_channel1_disabled = 2,
- .max_ddr3_freq = 1600,
- .usb_xhci_on_resume = 1,
- .usb2_ports = {
- /* Length, Enable, OCn#, Location */
- { 0x0080, 1, 0, /* P0: HOST PORT */
- USB_PORT_BACK_PANEL },
- { 0x0080, 1, 1, /* P1: HOST PORT */
- USB_PORT_BACK_PANEL },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P2: EMPTY */
- USB_PORT_SKIP },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: SD CARD */
- USB_PORT_INTERNAL },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P4: EMPTY */
- USB_PORT_SKIP },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: WWAN */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: CAMERA */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P7: BT */
- USB_PORT_INTERNAL },
- },
- .usb3_ports = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1: HOST PORT */
- { 1, 1 }, /* P2: HOST PORT */
- { 0, USB_OC_PIN_SKIP }, /* P3: EMPTY */
- { 1, USB_OC_PIN_SKIP }, /* P4: SD CARD */
- },
- };
+ romstage_common(rp);
- struct romstage_params romstage_params = {
- .pei_data = &pei_data,
- .gpio_map = &mainboard_gpio_map,
- .rcba_config = &rcba_config[0],
- .bist = bist,
- .copy_spd = copy_spd,
- };
-
- /* Call into the real romstage main with this board's attributes. */
- romstage_common(&romstage_params);
+ /*
+ * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
+ * to prevent possible brownout.
+ */
+ set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH);
}
diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c
index a525f16bb6..b43b46a427 100644
--- a/src/mainboard/google/samus/smihandler.c
+++ b/src/mainboard/google/samus/smihandler.c
@@ -21,16 +21,15 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
+#include <broadwell/pm.h>
+#include <broadwell/smm.h>
#include <elog.h>
-
-/* Include EC functions */
#include <ec/google/chromeec/ec.h>
+#include <broadwell/gpio.h>
+#include <broadwell/iomap.h>
+#include <broadwell/nvs.h>
+#include <broadwell/pm.h>
+#include <broadwell/smm.h>
#include "ec.h"
/* GPIO46 controls the WLAN_DISABLE_L signal. */
@@ -74,9 +73,9 @@ static u8 mainboard_smi_ec(void)
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
- pm1_cnt = inl(get_pmbase() + PM1_CNT);
+ pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
- outl(pm1_cnt, get_pmbase() + PM1_CNT);
+ outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
break;
}
@@ -97,12 +96,12 @@ void mainboard_smi_sleep(u8 slp_typ)
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
- if (smm_get_gnvs()->s3u0 == 0)
+ if (smm_get_gnvs()->s3u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
- if (smm_get_gnvs()->s3u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
+ }
/* Prevent leak from standby rail to WLAN rail in S3. */
set_gpio(GPIO_WLAN_DISABLE_L, 0);
@@ -113,12 +112,12 @@ void mainboard_smi_sleep(u8 slp_typ)
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
- if (smm_get_gnvs()->s5u0 == 0)
+ if (smm_get_gnvs()->s5u0 == 0) {
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
- if (smm_get_gnvs()->s5u1 == 0)
google_chromeec_set_usb_charge_mode(
1, USB_CHARGE_MODE_DISABLED);
+ }
/* Prevent leak from standby rail to WLAN rail in S5. */
set_gpio(GPIO_WLAN_DISABLE_L, 0);
@@ -138,25 +137,9 @@ void mainboard_smi_sleep(u8 slp_typ)
while (google_chromeec_get_event() != 0);
}
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
int mainboard_smi_apmc(u8 apmc)
{
switch (apmc) {
- case APMC_FINALIZE:
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "SMI#: Already finalized\n");
- return 0;
- }
-
- intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
- intel_cpu_haswell_finalize_smm();
-
- mainboard_finalized = 1;
- break;
case APM_CNT_ACPI_ENABLE:
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
diff --git a/src/mainboard/google/samus/spd.c b/src/mainboard/google/samus/spd.c
new file mode 100644
index 0000000000..4371da9bd8
--- /dev/null
+++ b/src/mainboard/google/samus/spd.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <broadwell/gpio.h>
+#include <broadwell/pei_data.h>
+#include <broadwell/romstage.h>
+#include "gpio.h"
+#include "spd.h"
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+ "density %d Mb\n", banks, ranks, rows, cols, capmb);
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int spd_gpio[3];
+ int spd_index;
+ int spd_file_len;
+ struct cbfs_file *spd_file;
+
+ spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+ spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+ spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+
+ spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
+
+ printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+ spd_index,
+ SPD_GPIO_BIT2, spd_gpio[2],
+ SPD_GPIO_BIT1, spd_gpio[1],
+ SPD_GPIO_BIT0, spd_gpio[0]);
+
+ spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
+ if (!spd_file)
+ die("SPD data not found.");
+ spd_file_len = ntohl(spd_file->len);
+
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ /* Assume same memory in both channels */
+ spd_index *= SPD_LEN;
+ memcpy(pei_data->spd_data[0][0],
+ ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
+ memcpy(pei_data->spd_data[1][0],
+ ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/samus/spd.h b/src/mainboard/google/samus/spd.h
new file mode 100644
index 0000000000..98180fa72c
--- /dev/null
+++ b/src/mainboard/google/samus/spd.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+
+/* Samus board memory configuration GPIOs */
+#define SPD_GPIO_BIT0 67
+#define SPD_GPIO_BIT1 68
+#define SPD_GPIO_BIT2 69
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/samus/thermal.h b/src/mainboard/google/samus/thermal.h
index 89069a62f2..9bea3f0c57 100644
--- a/src/mainboard/google/samus/thermal.h
+++ b/src/mainboard/google/samus/thermal.h
@@ -22,9 +22,6 @@
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
-/* Power level to set when EC requests throttle */
-#define EC_THROTTLE_POWER_LIMIT 12 /* 12W */
-
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 99
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 04:49:14 +0000