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Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/butterfly/chromeos.c37
-rw-r--r--src/mainboard/google/butterfly/gpio.c2
-rw-r--r--src/mainboard/google/butterfly/romstage.c2
-rw-r--r--src/mainboard/google/link/chromeos.c17
-rw-r--r--src/mainboard/google/link/gpio.c2
-rw-r--r--src/mainboard/google/link/mainboard.c1
-rw-r--r--src/mainboard/google/link/romstage.c3
-rw-r--r--src/mainboard/google/parrot/chromeos.c92
-rw-r--r--src/mainboard/google/parrot/gpio.c2
-rw-r--r--src/mainboard/google/parrot/romstage.c1
-rw-r--r--src/mainboard/google/stout/chromeos.c16
-rw-r--r--src/mainboard/google/stout/gpio.c2
-rw-r--r--src/mainboard/google/stout/romstage.c1
13 files changed, 31 insertions, 147 deletions
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 0b750b129a..69887f5a68 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <ec/quanta/ene_kb3940q/ec.h>
#include "ec.h"
@@ -29,9 +30,6 @@
#define FORCE_RECOVERY_MODE 0
#define FORCE_DEVELOPER_MODE 0
-
-int get_pch_gpio(unsigned char gpio_num);
-
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -92,38 +90,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}
#endif
-int get_pch_gpio(unsigned char gpio_num)
-{
- device_t dev;
- int retval = 0;
-
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return(0);
-
- if (gpio_num >= 64){
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- retval = ((gp_lvl3 >> (gpio_num - 64)) & 1);
- } else if (gpio_num >= 32){
- u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
- retval = ((gp_lvl2 >> (gpio_num - 32)) & 1);
- } else {
- u32 gp_lvl = inl(gpio_base + GP_LVL);
- retval = ((gp_lvl >> gpio_num) & 1);
- }
-
- return retval;
-}
-
int get_write_protect_state(void)
{
- return !get_pch_gpio(WP_GPIO);
+ return !get_gpio(WP_GPIO);
}
int get_lid_switch(void)
@@ -141,7 +110,7 @@ int get_developer_mode_switch(void)
#endif
/* Servo GPIO is active low, reverse it for intial state (request) */
- dev_mode = !get_pch_gpio(DEVMODE_GPIO);
+ dev_mode = !get_gpio(DEVMODE_GPIO);
printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO,
dev_mode);
diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c
index a08b787fb8..2d14699ef6 100644
--- a/src/mainboard/google/butterfly/gpio.c
+++ b/src/mainboard/google/butterfly/gpio.c
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_NONE, /* Unused */
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index a5aa793c16..050d5b0fd4 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -30,7 +30,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index 8b42828533..d07e8514e3 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
@@ -73,21 +74,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- //u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
-
- if (!gpio_base)
- return -1;
-
- u32 gp_lvl2 = inl(gpio_base + 0x38);
-
- return (gp_lvl2 >> (57 - 32)) & 1;
+ return get_gpio(57);
}
int get_lid_switch(void)
diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c
index ea6110e8f9..dcd29a33c6 100644
--- a/src/mainboard/google/link/gpio.c
+++ b/src/mainboard/google/link/gpio.c
@@ -16,7 +16,7 @@
#ifndef LINK_GPIO_H
#define LINK_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 3e241d46c4..922061f6da 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -32,6 +32,7 @@
#include "onboard.h"
#include "ec.h"
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 22b40a0f50..8142845bf2 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -30,8 +30,7 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/gpio.h>
-#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include "ec/google/chromeec/ec.h"
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index 82198a938d..c898f0e39c 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <ec/compal/ene932/ec.h>
#include "ec.h"
@@ -83,104 +84,41 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return 0;
-
- u32 gp_lvl = inl(gpio_base + GP_LVL);
- return (gp_lvl >> 15) & 1;
+ return get_gpio(15);
}
int get_developer_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+ u8 gpio = !get_gpio(17);
+ /*
+ * Dev mode is controlled by EC and uboot stores a flag in TPM.
+ * This GPIO is only for the debug header.
+ * It is AND'd to the EC request.
+ */
- if (!gpio_base)
- return(0);
-
-/*
- * Dev mode is controled by EC and uboot stores a flag in TPM. This GPIO is only
- * for the debug header. It is AND'd to the EC request.
- */
-
- u32 gp_lvl = inl(gpio_base + GP_LVL);
- printk(BIOS_DEBUG,"DEV MODE GPIO 17: %x\n", !((gp_lvl >> 17) & 1));
+ printk(BIOS_DEBUG, "DEV MODE GPIO 17: %x\n", gpio);
/* GPIO17, active low -- return active high reading and let
* it be inverted by the caller if needed. */
- return !((gp_lvl >> 17) & 1);
+ return gpio;
}
int get_write_protect_state(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return 0;
-
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
-
- return !((gp_lvl3 >> (70 - 64)) & 1);
+ return !get_gpio(70);
}
int get_recovery_mode_switch(void)
{
- u8 rec_mode;
-
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return(0);
-
+ u8 gpio = !get_gpio(68);
/* GPIO68, active low. For Servo support
* Treat as active high and let the caller invert if needed. */
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- rec_mode = !((gp_lvl3 >> (68 - 64)) & 1);
- printk(BIOS_DEBUG,"REC MODE GPIO 68: %x\n", rec_mode);
+ printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio);
- return (rec_mode);
+ return gpio;
}
int parrot_ec_running_ro(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return(0);
-
- /* GPIO68 EC_RW is active low.
- * Treat as active high and let the caller invert if needed. */
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
- return !((gp_lvl3 >> (68 - 64)) & 1);
+ return !get_gpio(68);
}
diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c
index c3e3e2fbe7..8ad18f1f51 100644
--- a/src/mainboard/google/parrot/gpio.c
+++ b/src/mainboard/google/parrot/gpio.c
@@ -16,7 +16,7 @@
#ifndef PARROT_GPIO_H
#define PARROT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_NONE, /* NOT USED */
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 5897d13bcf..135cc766f1 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -30,6 +30,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index a2abaed24a..4c7a9f5037 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -21,6 +21,7 @@
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include "ec.h"
#include <ec/quanta/it8518/ec.h>
@@ -81,20 +82,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
- if (!gpio_base)
- return 0;
-
- u32 gp_lvl = inl(gpio_base + GP_LVL);
-
- return !((gp_lvl >> 7) & 1);
+ return !get_gpio(7);
}
int get_lid_switch(void)
diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c
index 7fffe8b48b..43134ea264 100644
--- a/src/mainboard/google/stout/gpio.c
+++ b/src/mainboard/google/stout/gpio.c
@@ -16,7 +16,7 @@
#ifndef STOUT_GPIO_H
#define STOUT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* GPIO0 */
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 983988ce5d..8348e4f158 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -30,6 +30,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 21:04:19 +0000