diff options
Diffstat (limited to 'src/mainboard/google')
11 files changed, 720 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d840426c76..2981ea78f6 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -482,6 +482,15 @@ config BOARD_GOOGLE_RIVEN select SOC_INTEL_TWINLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS +config BOARD_GOOGLE_RULL + select BOARD_GOOGLE_BASEBOARD_NISSA + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GFX_GENERIC + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_SKOLAS select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_NAU8315 @@ -727,6 +736,7 @@ config DRIVER_TPM_I2C_BUS default 0x1 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX4ES default 0x0 if BOARD_GOOGLE_RIVEN + default 0x0 if BOARD_GOOGLE_RULL default 0x1 if BOARD_GOOGLE_SKOLAS default 0x1 if BOARD_GOOGLE_SKOLAS4ES default 0x1 if BOARD_GOOGLE_TAEKO @@ -802,6 +812,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_REDRIX default 13 if BOARD_GOOGLE_REDRIX4ES default 13 if BOARD_GOOGLE_RIVEN + default 13 if BOARD_GOOGLE_RULL default 13 if BOARD_GOOGLE_SKOLAS default 13 if BOARD_GOOGLE_SKOLAS4ES default 13 if BOARD_GOOGLE_TAEKO @@ -881,6 +892,7 @@ config MAINBOARD_PART_NUMBER default "Redrix" if BOARD_GOOGLE_REDRIX default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES default "Riven" if BOARD_GOOGLE_RIVEN + default "Rull" if BOARD_GOOGLE_RULL default "Skolas" if BOARD_GOOGLE_SKOLAS default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES default "Sundance" if BOARD_GOOGLE_SUNDANCE @@ -951,6 +963,7 @@ config VARIANT_DIR default "redrix" if BOARD_GOOGLE_REDRIX default "redrix4es" if BOARD_GOOGLE_REDRIX4ES default "riven" if BOARD_GOOGLE_RIVEN + default "rull" if BOARD_GOOGLE_RULL default "skolas" if BOARD_GOOGLE_SKOLAS default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES default "sundance" if BOARD_GOOGLE_SUNDANCE diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b263642968..1beee8dd07 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -128,6 +128,9 @@ config BOARD_GOOGLE_REDRIX4ES config BOARD_GOOGLE_RIVEN bool "-> Riven" +config BOARD_GOOGLE_RULL + bool "-> Rull" + config BOARD_GOOGLE_SKOLAS bool "-> Skolas" diff --git a/src/mainboard/google/brya/variants/rull/Makefile.mk b/src/mainboard/google/brya/variants/rull/Makefile.mk new file mode 100644 index 0000000000..f41cdfdb8a --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c new file mode 100644 index 0000000000..13d64690d8 --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : NC ==> LTE_Present */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : GPP_A8 ==> NC */ + PAD_NC_LOCK(GPP_A8, NONE, LOCK_CONFIG), + /* A11 : GPP_A11 ==> EN_SPK_PA */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* A18 : NC ==> HDMI_HPD_SRC*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* A21 : GPP_A21 ==> NC */ + PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG), + /* A22 : GPP_A22 ==> NC */ + PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), + + /* B4 : I2C2_SDA ==> SSD1_RST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), + /* B5 : I2C2_SDA ==> NA */ + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), + /* B6 : I2C2_SCL ==> NA */ + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), + /* B11 : NC ==> EN_PP3300_WLAN_X*/ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + + /* D3 : ISH_GP3 ==> NA */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D6 : WWAN_PWR_ENABLE ==> PCIE_REFCLK_SSD1_REQ_N */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), + /* D11 : EN_PP1800_WCAM_X ==> EN_PP3300_SSD_X */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D13 : EN_PP1800_WCAM_X ==> NA */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D15 : EN_PP2800_WCAM_X ==> NA */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : EN_PP1800_PP1200_WCAM_X ==> NA */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + + /* E4 : NA ==> SSD/EMMC/UFS ID */ + PAD_CFG_GPI_LOCK(GPP_E4, NONE, LOCK_CONFIG), + /* E5 : NA ==> SSD/EMMC/UFS ID */ + PAD_CFG_GPI_LOCK(GPP_E5, NONE, LOCK_CONFIG), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + + /* F12 : WWAN_RST_L ==> NA */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : SOC_PEN_DETECT_R_ODL ==> NA */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : SOC_PEN_DETECT_ODL ==> NA */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F23 : V1P05_CTRL ==> NC*/ + PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), + + + /* H12 : UART0_RTS# ==> NC*/ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H22 : WCAM_MCLK_R ==> NA */ + PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL ==> NA */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), + + /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + + /* F11 : NC ==> WWAN_PWR_ON */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/rull/include/variant/ec.h b/src/mainboard/google/brya/variants/rull/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/rull/include/variant/gpio.h b/src/mainboard/google/brya/variants/rull/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk new file mode 100644 index 0000000000..33cf7f9c8e --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/rull/memory src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 3(0b0011) Parts = H58G66BK8BX067 diff --git a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt new file mode 100644 index 0000000000..9a4250c3bc --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/rull/memory src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 0 (0000) +K3KL8L80CM-MGCT 1 (0001) +H58G56BK7BX068 1 (0001) +K3KL9L90CM-MGCT 2 (0010) +H58G66BK8BX067 3 (0011) diff --git a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt new file mode 100644 index 0000000000..6b13e72595 --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +K3KL8L80CM-MGCT +H58G56BK7BX068 +K3KL9L90CM-MGCT +H58G66BK8BX067 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb new file mode 100644 index 0000000000..d91a7aaaae --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -0,0 +1,429 @@ +fw_config + field THERMAL 18 18 + option THERMAL_6W 0 + option THERMAL_15W 1 + end + field WIFI 8 9 + option WIFI_CNVI_WIFI6E 0 + option WIFI_PCIE_WIFI7 1 + end + +end + +chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0100b + # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB. + # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB. + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{ + .pad_auxp_dc = GPP_A19, + .pad_auxn_dc = GPP_A20 + }" + + register "typec_aux_bias_pads[1]" = "{ + .pad_auxp_dc = GPP_E22, + .pad_auxn_dc = GPP_E23 + }" + + # FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 0, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------+------------------------------+ + #| Field | Value | + #+-------------+------------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------+------------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 152, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + # Power limit config + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU_VR"" + register "options.tsr[1].desc" = ""CPU"" + register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + # Internal panel on the first port of the graphics chip + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + device ref i2c1 off end # Touchscreen + device ref i2c3 on + chip drivers/i2c/rt5645 + register "hid" = ""10EC5650"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5650"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "jd_mode" = "2" + device i2c 1a on end + end + end + device ref i2c5 off end # Touchpad + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI_WIFI6E + probe unprovisioned + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + probe WIFI WIFI_PCIE_WIFI7 + probe unprovisioned + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch) + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch) + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch) + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE) + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""PCIe Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on + probe WIFI WIFI_CNVI_WIFI6E + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + device ref pcie_rp7 off end # SDCard + device ref pcie_rp9 on + # Enable NVMe SSD PCIe 9-12 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, + }" + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is EN_PP3300_SSD + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D11)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe STORAGE STORAGE_NVME + probe unprovisioned + end + device ref emmc on + probe STORAGE STORAGE_EMMC + probe unprovisioned + end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "rt5650_sp" + register "jack_tplg" = "rt5650_hp" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c new file mode 100644 index 0000000000..a2fffb4ba3 --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> +#include <soc/gpio_soc_defs.h> +#include <intelblocks/graphics.h> + +/* Per-pipe DDI Function Control 2 */ +#define TRANS_DDI_FUNC_CTL2_A 0x60404 +#define TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS (3 << 6) + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} + +static const struct pad_config wifi_pcie_enable_pad[] = { + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* B11 : NC ==> EN_PP3300_WLAN_X*/ + PAD_CFG_GPO(GPP_B11, 1, DEEP), +}; + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_is_provisioned()) { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); + config->cnvi_bt_audio_offload = false; + } +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || !fw_config_is_provisioned()) { + printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); + gpio_padbased_override(padbased_table, wifi_pcie_enable_pad, + ARRAY_SIZE(wifi_pcie_enable_pad)); + } +} + +void variant_finalize(void) +{ + /* + * Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, + * it is because it inserts 12 blank frames if it receives the unmute in VB-ID. + * + * Always override the mute in VB-ID to avoid Tcon EC detected the + * audiomute_flag change. + */ + graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS, + TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS); +} |