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-rw-r--r--src/mainboard/google/fatcat/chromeos-debug-fsp.fmd18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
index f34e495c2d..8d41977735 100644
--- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
+++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
@@ -9,6 +9,15 @@ FLASH 32M {
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
+ # This section starts at the 16M boundary in SPI flash.
+ # PTL does not support a region crossing this boundary,
+ # because the SPI flash is memory-mapped into two non-
+ # contiguous windows.
+ RW_SECTION_B 7680K {
+ VBLOCK_B 8K
+ FW_MAIN_B(CBFS)
+ RW_FWID_B 64
+ }
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
@@ -22,15 +31,6 @@ FLASH 32M {
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
- # This section starts at the 16M boundary in SPI flash.
- # MTL does not support a region crossing this boundary,
- # because the SPI flash is memory-mapped into two non-
- # contiguous windows.
- RW_SECTION_B 7680K {
- VBLOCK_B 8K
- FW_MAIN_B(CBFS)
- RW_FWID_B 64
- }
RW_LEGACY(CBFS) 1M
RW_UNUSED 2M
# Make WP_RO region align with SPI vendor