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-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb86
-rw-r--r--src/mainboard/google/fizz/variants/endeavour/overridetree.cb24
-rw-r--r--src/mainboard/google/fizz/variants/fizz/overridetree.cb8
-rw-r--r--src/mainboard/google/fizz/variants/karma/overridetree.cb10
4 files changed, 54 insertions, 74 deletions
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 46069ced39..44fc014a9b 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -307,10 +307,9 @@ chip soc/intel/skylake
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on end # SA thermal subsystem
- device pci 14.0 on
+ device ref igpu on end
+ device ref sa_thermal on end
+ device ref south_xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
@@ -362,78 +361,59 @@ chip soc/intel/skylake
end
end
end
- end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Thermal Subsystem
- device pci 14.3 off end # Camera
- device pci 15.0 on end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 on end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 17.0 on end # SATA
- device pci 19.0 on end # UART #2
- device pci 19.1 on end # I2C #5
- device pci 19.2 off end # I2C #4
- device pci 1c.0 on end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP
- device pci 1c.2 on
+ end
+ device ref thermal on end
+ device ref i2c0 on end
+ device ref i2c2 on end
+ device ref heci1 on end
+ device ref sata on end
+ device ref uart2 on end
+ device ref i2c5 on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp3 on
+ # LAN, will be swapped to port 1 by FSP
chip drivers/net
register "customized_leds" = "0x0fa5"
register "wake" = "GPE0_PCI_EXP"
device pci 00.0 on end
register "device_index" = "0"
end
- end # PCI Express Port 3
- device pci 1c.3 on
+ end
+ device ref pcie_rp4 on
+ # WLAN
chip drivers/wifi/generic
register "wake" = "GPE0_PCI_EXP"
device pci 00.0 on end
end
- end # PCI Express Port 4 for WLAN
- device pci 1c.4 on end # PCI Express Port 5 for NVMe
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9 for 2nd LAN
+ end
+ device ref pcie_rp5 on end # NVMe
+ device ref pcie_rp9 on
+ # 2nd LAN
chip drivers/net
register "customized_leds" = "0x0fa5"
register "device_index" = "1"
device pci 00.0 on end
end
- end # PCI Express Port 9 for BtoB
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 on end # PCI Express Port 11
- device pci 1d.3 on end # PCI Express Port 12
- device pci 1e.0 on end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 on
+ end
+ device ref pcie_rp11 on end
+ device ref pcie_rp12 on end
+ device ref uart0 on end
+ device ref gspi0 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device spi 0 on end
end
- end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1e.4 off end # eMMC
- device pci 1e.5 off end # SDIO
- device pci 1e.6 on end # SDCard
- device pci 1f.0 on
+ end
+ device ref sdxc on end
+ device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
- end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ end
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
end
end
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 07ed7bcae4..989b2406fb 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -77,7 +77,7 @@ chip soc/intel/skylake
}"
device domain 0 on
- device pci 14.0 on
+ device ref south_xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -128,8 +128,8 @@ chip soc/intel/skylake
device usb 3.5 off end
end
end
- end # USB xHCI
- device pci 15.3 on
+ end
+ device ref i2c3 on
chip drivers/i2c/generic
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "desc" = ""Chrontel 7322""
@@ -146,8 +146,8 @@ chip soc/intel/skylake
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
device i2c 76 on end
end
- end # I2C #3
- device pci 19.1 on
+ end
+ device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""10EC5663""
register "name" = ""RT53""
@@ -155,12 +155,12 @@ chip soc/intel/skylake
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
device i2c 13 on end
end
- end # I2C #5
- device pci 1c.6 on end # PCI Express Port 7 for TPU1
- device pci 1c.7 on end # PCI Express Port 8 for TPU0
- device pci 1d.0 on end # PCI Express Port 9 for POE LAN
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
+ end
+ device ref pcie_rp7 on end # TPU1
+ device ref pcie_rp8 on end # TPU0
+ device ref pcie_rp9 on end # POE LAN
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
end
end
diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb
index b4eea385e0..e17d148af6 100644
--- a/src/mainboard/google/fizz/variants/fizz/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb
@@ -8,7 +8,7 @@ chip soc/intel/skylake
register "SaGv" = "SaGv_FixedHigh"
device domain 0 on
- device pci 14.0 on
+ device ref south_xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -33,8 +33,8 @@ chip soc/intel/skylake
end
end
end
- end # USB xHCI
- device pci 19.1 on
+ end
+ device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""10EC5663""
register "name" = ""RT53""
@@ -42,6 +42,6 @@ chip soc/intel/skylake
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
device i2c 13 on end
end
- end # I2C #5
+ end
end
end
diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb
index 1dba50c09b..d1dc46f45a 100644
--- a/src/mainboard/google/fizz/variants/karma/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb
@@ -22,7 +22,7 @@ chip soc/intel/skylake
}"
device domain 0 on
- device pci 14.0 on
+ device ref south_xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -57,8 +57,8 @@ chip soc/intel/skylake
end
end
end
- end # USB xHCI
- device pci 19.1 on
+ end
+ device ref i2c5 on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
@@ -82,7 +82,7 @@ chip soc/intel/skylake
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
- end # I2C #5
- device pci 1e.6 off end # SDCard
+ end
+ device ref sdxc off end
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 16:43:29 +0000