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-rw-r--r--src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index fd2c8ed72f..be31df6837 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -23,9 +23,6 @@ chip soc/intel/alderlake
register "tcc_offset" = "10" # TCC of 90
- # Enable CNVi BT
- register "cnvi_bt_core" = "true"
-
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2