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-rw-r--r--src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb8
-rw-r--r--src/mainboard/google/brox/variants/brox/overridetree.cb14
2 files changed, 4 insertions, 18 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index a82b4f0994..22e15aca89 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -160,11 +160,11 @@ chip soc/intel/alderlake
}"
end
device ref dtt on end
- device ref tbt_pcie_rp0 on end
- device ref tbt_pcie_rp2 on end
+ device ref tbt_pcie_rp0 off end
+ device ref tbt_pcie_rp2 off end
device ref tcss_xhci on end
- device ref tcss_dma0 on end
- device ref tcss_dma1 on end
+ device ref tcss_dma0 off end
+ device ref tcss_dma1 off end
device ref xhci on end
device ref shared_sram on end
device ref i2c0 on
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index 18baa5d590..37c4e0120b 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -268,20 +268,6 @@ chip soc/intel/alderlake
end
end
end
- device ref tcss_dma0 on
- chip drivers/intel/usb4/retimer
- register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
- use tcss_usb3_port1 as dfp[0].typec_port
- device generic 0 on end
- end
- end
- device ref tcss_dma1 on
- chip drivers/intel/usb4/retimer
- register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
- use tcss_usb3_port3 as dfp[0].typec_port
- device generic 0 on end
- end
- end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 3
register "cpu_pcie_rp[CPU_RP(1)]" = "{