diff options
Diffstat (limited to 'src/mainboard/google')
37 files changed, 130 insertions, 115 deletions
diff --git a/src/mainboard/google/daisy/Makefile.inc b/src/mainboard/google/daisy/Makefile.inc index df9b797367..1f041abc9e 100644 --- a/src/mainboard/google/daisy/Makefile.inc +++ b/src/mainboard/google/daisy/Makefile.inc @@ -26,3 +26,7 @@ romstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += chromeos.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 5840e51049..138e498de8 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -36,20 +36,17 @@ #include <soc/samsung/exynos5250/dp.h> #include <soc/samsung/exynos5250/periph.h> #include <soc/samsung/exynos5250/usb.h> +#include <symbols.h> #include "exynos5250.h" #define MMC0_GPIO_PIN (58) /* convenient shorthand (in MB) */ -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_START ((uintptr_t)_dram/MiB) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ -/* Arbitrary range of DMA memory for depthcharge's drivers */ -#define DMA_START (0x77300000) -#define DMA_SIZE (0x00100000) - static struct edid edid = { .ha = 1366, .va = 768, @@ -333,7 +330,8 @@ static void mainboard_enable(device_t dev) mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_mmu_enable(); @@ -359,6 +357,6 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = (intptr_t)DMA_START; - dma->range_size = DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } diff --git a/src/mainboard/google/daisy/memlayout.ld b/src/mainboard/google/daisy/memlayout.ld new file mode 100644 index 0000000000..72c018edd2 --- /dev/null +++ b/src/mainboard/google/daisy/memlayout.ld @@ -0,0 +1 @@ +#include <soc/samsung/exynos5250/memlayout.ld> diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 864e577c3d..082985d211 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -42,14 +42,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan" -config DRAM_DMA_START - hex - default 0x90000000 - -config DRAM_DMA_SIZE - hex - default 0x00200000 - choice prompt "BCT boot media" default NYAN_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 7ac11e8a33..6506abaf6e 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -42,3 +42,7 @@ ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index b534ea908d..e52db83d18 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -30,6 +30,7 @@ #include <soc/nvidia/tegra124/pmc.h> #include <soc/nvidia/tegra124/spi.h> #include <soc/nvidia/tegra/usb.h> +#include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; @@ -268,6 +269,6 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = CONFIG_DRAM_DMA_START; - dma->range_size = CONFIG_DRAM_DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } diff --git a/src/mainboard/google/nyan/memlayout.ld b/src/mainboard/google/nyan/memlayout.ld new file mode 100644 index 0000000000..33ce6446ad --- /dev/null +++ b/src/mainboard/google/nyan/memlayout.ld @@ -0,0 +1 @@ +#include <soc/nvidia/tegra124/memlayout.ld> diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 1ff500b5d3..f2077bbb27 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -39,6 +39,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> +#include <symbols.h> #include <timestamp.h> static void __attribute__((noinline)) romstage(void) @@ -52,24 +53,25 @@ static void __attribute__((noinline)) romstage(void) sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ - u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ - u32 dram_size = dram_end - dram_start; + u32 dram_start_mb = (uintptr_t)_dram/MiB; + u32 dram_end_mb = sdram_max_addressable_mb(); + u32 dram_size_mb = dram_end_mb - dram_start_mb; configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start, DCACHE_OFF); - /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ - mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start_mb, DCACHE_OFF); + /* SRAM is cached. MMU code will round size up to page size. */ + mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + DCACHE_WRITEBACK); /* DRAM is cached. */ - mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ - mmu_config_range(CONFIG_DRAM_DMA_START >> 20, - CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ - if (dram_end < 4096) - mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + if (dram_end_mb < 4096) + mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 2968b0142e..7334472e41 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -44,14 +44,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan Big" -config DRAM_DMA_START - hex - default 0x90000000 - -config DRAM_DMA_SIZE - hex - default 0x00200000 - choice prompt "BCT boot media" default NYAN_BIG_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index 8ca495ce55..fddb44e0e1 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -41,3 +41,7 @@ ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 86d9fe3b37..05f6faeef1 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -30,6 +30,7 @@ #include <soc/nvidia/tegra124/pmc.h> #include <soc/nvidia/tegra124/spi.h> #include <soc/nvidia/tegra/usb.h> +#include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; @@ -266,6 +267,6 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = CONFIG_DRAM_DMA_START; - dma->range_size = CONFIG_DRAM_DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } diff --git a/src/mainboard/google/nyan_big/memlayout.ld b/src/mainboard/google/nyan_big/memlayout.ld new file mode 100644 index 0000000000..33ce6446ad --- /dev/null +++ b/src/mainboard/google/nyan_big/memlayout.ld @@ -0,0 +1 @@ +#include <soc/nvidia/tegra124/memlayout.ld> diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 1ff500b5d3..f2077bbb27 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -39,6 +39,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> +#include <symbols.h> #include <timestamp.h> static void __attribute__((noinline)) romstage(void) @@ -52,24 +53,25 @@ static void __attribute__((noinline)) romstage(void) sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ - u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ - u32 dram_size = dram_end - dram_start; + u32 dram_start_mb = (uintptr_t)_dram/MiB; + u32 dram_end_mb = sdram_max_addressable_mb(); + u32 dram_size_mb = dram_end_mb - dram_start_mb; configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start, DCACHE_OFF); - /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ - mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start_mb, DCACHE_OFF); + /* SRAM is cached. MMU code will round size up to page size. */ + mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + DCACHE_WRITEBACK); /* DRAM is cached. */ - mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ - mmu_config_range(CONFIG_DRAM_DMA_START >> 20, - CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ - if (dram_end < 4096) - mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + if (dram_end_mb < 4096) + mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 5938e7ee1c..34959199b3 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -45,14 +45,6 @@ config MAINBOARD_PART_NUMBER string default "Nyan Blaze" -config DRAM_DMA_START - hex - default 0x90000000 - -config DRAM_DMA_SIZE - hex - default 0x00200000 - choice prompt "BCT boot media" default NYAN_BLAZE_BCT_CFG_SPI diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index dc998d1c2d..343040994c 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -45,3 +45,8 @@ ramstage-y += reset.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index ccbaf63f94..5f1cb49ceb 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -30,6 +30,7 @@ #include <soc/nvidia/tegra124/pmc.h> #include <soc/nvidia/tegra124/spi.h> #include <soc/nvidia/tegra/usb.h> +#include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; @@ -266,6 +267,6 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = CONFIG_DRAM_DMA_START; - dma->range_size = CONFIG_DRAM_DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } diff --git a/src/mainboard/google/nyan_blaze/memlayout.ld b/src/mainboard/google/nyan_blaze/memlayout.ld new file mode 100644 index 0000000000..33ce6446ad --- /dev/null +++ b/src/mainboard/google/nyan_blaze/memlayout.ld @@ -0,0 +1 @@ +#include <soc/nvidia/tegra124/memlayout.ld> diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index fca705df03..fb1b9e2b77 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -39,6 +39,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> +#include <symbols.h> #include <timestamp.h> static void __attribute__((noinline)) romstage(void) @@ -52,29 +53,30 @@ static void __attribute__((noinline)) romstage(void) sdram_init(get_sdram_config()); /* used for MMU and CBMEM setup, in MB */ - u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ - u32 dram_size = dram_end - dram_start; + u32 dram_start_mb = (uintptr_t)_dram/MiB; + u32 dram_end_mb = sdram_max_addressable_mb(); + u32 dram_size_mb = dram_end_mb - dram_start_mb; #if !CONFIG_VBOOT2_VERIFY_FIRMWARE configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start, DCACHE_OFF); - /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ - mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + mmu_config_range(0, dram_start_mb, DCACHE_OFF); + /* SRAM is cached. MMU code will round size up to page size. */ + mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB), + DCACHE_WRITEBACK); /* The space above DRAM is uncached. */ - if (dram_end < 4096) - mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + if (dram_end_mb < 4096) + mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); mmu_disable_range(0, 1); dcache_mmu_enable(); #endif /* DRAM is cached. */ - mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ - mmu_config_range(CONFIG_DRAM_DMA_START >> 20, - CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); /* * A watchdog reset only resets part of the system so it ends up in diff --git a/src/mainboard/google/peach_pit/Makefile.inc b/src/mainboard/google/peach_pit/Makefile.inc index df9b797367..1f041abc9e 100644 --- a/src/mainboard/google/peach_pit/Makefile.inc +++ b/src/mainboard/google/peach_pit/Makefile.inc @@ -26,3 +26,7 @@ romstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += chromeos.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1a15bd2347..b6f49e2942 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -40,15 +40,12 @@ #include <drivers/parade/ps8625/ps8625.h> #include <ec/google/chromeec/ec.h> #include <stdlib.h> +#include <symbols.h> /* convenient shorthand (in MB) */ -#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_START ((uintptr_t)_dram/MiB) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB -/* Arbitrary range of DMA memory for depthcharge's drivers */ -#define DMA_START (0x77300000) -#define DMA_SIZE (0x00100000) - static struct edid edid = { .ha = 1366, .va = 768, @@ -469,7 +466,8 @@ static void mainboard_enable(device_t dev) /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); - mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); const unsigned epll_hz = 192000000; const unsigned sample_rate = 48000; @@ -493,6 +491,6 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = (intptr_t)DMA_START; - dma->range_size = DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } diff --git a/src/mainboard/google/peach_pit/memlayout.ld b/src/mainboard/google/peach_pit/memlayout.ld new file mode 100644 index 0000000000..565ba89194 --- /dev/null +++ b/src/mainboard/google/peach_pit/memlayout.ld @@ -0,0 +1 @@ +#include <soc/samsung/exynos5420/memlayout.ld> diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc index 2a1ce99527..e41745f1a1 100644 --- a/src/mainboard/google/rush/Makefile.inc +++ b/src/mainboard/google/rush/Makefile.inc @@ -40,3 +40,7 @@ ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld new file mode 100644 index 0000000000..b9def51e74 --- /dev/null +++ b/src/mainboard/google/rush/memlayout.ld @@ -0,0 +1 @@ +#include <soc/nvidia/tegra132/memlayout.ld> diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc index 2fe12a4ea1..67a3facaba 100644 --- a/src/mainboard/google/rush_ryu/Makefile.inc +++ b/src/mainboard/google/rush_ryu/Makefile.inc @@ -41,3 +41,7 @@ ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c ramstage-y += chromeos.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld new file mode 100644 index 0000000000..b9def51e74 --- /dev/null +++ b/src/mainboard/google/rush_ryu/memlayout.ld @@ -0,0 +1 @@ +#include <soc/nvidia/tegra132/memlayout.ld> diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index b0c064c919..3e1e0168bb 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -48,12 +48,4 @@ config DRAM_SIZE_MB default 512 if BOARD_VARIANT_AP148 default 1024 -config DRAM_DMA_START - hex - default 0x5a000000 - -config DRAM_DMA_SIZE - hex - default 0x00200000 - endif # BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index 907638a3ef..6ee0841dc3 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -25,3 +25,7 @@ romstage-y += cdp.c ramstage-y += boardid.c ramstage-y += cdp.c ramstage-y += mainboard.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 3da6f905b2..478e2a8b8d 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -25,19 +25,20 @@ #include <device/device.h> #include <gpiolib.h> #include <string.h> +#include <symbols.h> #include <soc/qualcomm/ipq806x/include/clock.h> #include <soc/qualcomm/ipq806x/include/gpio.h> #include <soc/qualcomm/ipq806x/include/usb.h> /* convenient shorthand (in MB) */ -#define DRAM_START (CONFIG_SYS_SDRAM_BASE / MiB) +#define DRAM_START ((uintptr_t)_dram / MiB) #define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) #define DRAM_END (DRAM_START + DRAM_SIZE) /* DMA memory for drivers */ -#define DMA_START (CONFIG_DRAM_DMA_START / MiB) -#define DMA_SIZE (CONFIG_DRAM_DMA_SIZE / MiB) +#define DMA_START ((uintptr_t)_dma_coherent / MiB) +#define DMA_SIZE (_dma_coherent_size / MiB) #define USB_ENABLE_GPIO 51 @@ -134,8 +135,8 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = CONFIG_DRAM_DMA_START; - dma->range_size = CONFIG_DRAM_DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } static int read_gpio(gpio_t gpio_num) diff --git a/src/mainboard/google/storm/memlayout.ld b/src/mainboard/google/storm/memlayout.ld new file mode 100644 index 0000000000..1735835321 --- /dev/null +++ b/src/mainboard/google/storm/memlayout.ld @@ -0,0 +1 @@ +#include <soc/qualcomm/ipq806x/memlayout.ld> diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index bde26d6524..a9363f969e 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -38,10 +38,6 @@ config MAINBOARD_PART_NUMBER string default "ImgTec Pistachio Virtual Platform" -config SYS_SDRAM_BASE - hex "SDRAM base address" - default 0x80000000 - config DRAM_SIZE_MB int default 256 diff --git a/src/mainboard/google/urara/Makefile.inc b/src/mainboard/google/urara/Makefile.inc index 4ce6398a2b..5a9dc0216f 100644 --- a/src/mainboard/google/urara/Makefile.inc +++ b/src/mainboard/google/urara/Makefile.inc @@ -21,3 +21,6 @@ ramstage-y += mainboard.c +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld new file mode 100644 index 0000000000..ab0b4dd8ff --- /dev/null +++ b/src/mainboard/google/urara/memlayout.ld @@ -0,0 +1 @@ +#include <soc/imgtec/pistachio/memlayout.ld> diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 97a009730a..7c4f084a99 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -61,14 +61,6 @@ config BOOT_MEDIA_SPI_BUS int default 2 -config DRAM_DMA_START - hex - default 0x10000000 - -config DRAM_DMA_SIZE - hex - default 0x00200000 - config DRAM_SIZE_MB int default 2048 diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc index c33cfa3166..0cc89d0222 100644 --- a/src/mainboard/google/veyron_pinky/Makefile.inc +++ b/src/mainboard/google/veyron_pinky/Makefile.inc @@ -35,3 +35,8 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c index 232010ddd9..19d66757ba 100644 --- a/src/mainboard/google/veyron_pinky/mainboard.c +++ b/src/mainboard/google/veyron_pinky/mainboard.c @@ -22,6 +22,7 @@ #include <arch/cache.h> #include <delay.h> #include <edid.h> +#include <symbols.h> #include <vbe.h> #include <boot/coreboot_tables.h> #include <device/i2c.h> @@ -153,6 +154,6 @@ void lb_board(struct lb_header *header) dma = (struct lb_range *)lb_new_record(header); dma->tag = LB_TAB_DMA; dma->size = sizeof(*dma); - dma->range_start = CONFIG_DRAM_DMA_START; - dma->range_size = CONFIG_DRAM_DMA_SIZE; + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; } diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld new file mode 100644 index 0000000000..a8b7465c5e --- /dev/null +++ b/src/mainboard/google/veyron_pinky/memlayout.ld @@ -0,0 +1 @@ +#include <soc/rockchip/rk3288/memlayout.ld> diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index f972ee26c8..1d7812b3e0 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -35,6 +35,7 @@ #include <soc/rockchip/rk3288/clock.h> #include <soc/rockchip/rk3288/pwm.h> #include <soc/rockchip/rk3288/grf.h> +#include <symbols.h> #include "timer.h" static void regulate_vdd_log(unsigned int mv) @@ -64,9 +65,9 @@ void main(void) start_romstage_time = timestamp_get(); #endif /* used for MMU and CBMEM setup, in MB */ - u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_size = CONFIG_DRAM_SIZE_MB; - u32 dram_end = dram_start + dram_size; + u32 dram_start_mb = (uintptr_t)_dram/MiB; + u32 dram_size_mb = CONFIG_DRAM_SIZE_MB; + u32 dram_end_mb = dram_start_mb + dram_size_mb; console_init(); @@ -81,15 +82,15 @@ void main(void) #endif mmu_init(); /* Device memory below DRAM is uncached. */ - mmu_config_range(0, dram_start, DCACHE_OFF); + mmu_config_range(0, dram_start_mb, DCACHE_OFF); /* DRAM is cached. */ - mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK); /* A window for DMA is uncached. */ - mmu_config_range(CONFIG_DRAM_DMA_START >> 20, - CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); /* The space above DRAM is uncached. */ - if (dram_end < 4096) - mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + if (dram_end_mb < 4096) + mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF); dcache_mmu_enable(); cbmem_initialize_empty(); |