diff options
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/butterfly/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/parrot/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/stout/romstage.c | 5 |
4 files changed, 8 insertions, 12 deletions
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index ebcba8409c..3ef4659a5a 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -96,9 +95,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index cc2ef22ab6..d9f00f4bc3 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -30,7 +30,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> @@ -104,9 +103,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); } static uint8_t *locate_spd(void) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 30fa7c22b8..6163c35e02 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -95,9 +94,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 9ad03f7366..36ebcf7d36 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> @@ -101,9 +100,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); |