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-rw-r--r--src/mainboard/google/butterfly/romstage.c4
-rw-r--r--src/mainboard/google/link/gpio.h2
-rw-r--r--src/mainboard/google/link/romstage.c103
-rw-r--r--src/mainboard/google/parrot/gpio.h2
-rw-r--r--src/mainboard/google/parrot/romstage.c98
-rw-r--r--src/mainboard/google/stout/gpio.h2
-rw-r--r--src/mainboard/google/stout/romstage.c113
7 files changed, 56 insertions, 268 deletions
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 40b5e762dc..65a294c555 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -131,3 +131,7 @@ void mainboard_get_spd(spd_raw_data *spd) {
void mainboard_early_init(int s3resume) {
}
+
+void mainboard_config_superio(void)
+{
+}
diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h
index 1dab97e75e..ea6110e8f9 100644
--- a/src/mainboard/google/link/gpio.h
+++ b/src/mainboard/google/link/gpio.h
@@ -98,7 +98,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = {
const struct pch_gpio_set3 pch_gpio_set3_level = {
};
-const struct pch_gpio_map link_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index a0970df562..2f40ba5186 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -33,7 +33,6 @@
#include <southbridge/intel/bd82x6x/gpio.h>
#include "ec/google/chromeec/ec.h"
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <halt.h>
#include "gpio.h"
@@ -42,7 +41,7 @@
#include <southbridge/intel/bd82x6x/chip.h>
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
const struct device *lpc;
const struct southbridge_intel_bd82x6x_config *config = NULL;
@@ -68,7 +67,7 @@ static void pch_enable_lpc(void)
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
-static void rcba_config(void)
+void rcba_config(void)
{
u32 reg32;
@@ -144,13 +143,9 @@ static void copy_spd(struct pei_data *peid)
sizeof(peid->spd_data[0]));
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- int boot_mode = 0;
- int cbmem_was_initted;
-
- struct pei_data pei_data = {
+ struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -195,89 +190,25 @@ void main(unsigned long bist)
{ 0, 4, 0x0000 }, /* P13: Empty */
},
};
+ *pei_data = pei_data_template;
+ copy_spd(pei_data);
+}
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
- setup_pch_gpios(&link_gpio_map);
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- printk(BIOS_DEBUG, "soft reset detected\n");
- boot_mode = 1;
-
- /* System is not happy after keyboard reset... */
- printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
- outb(0x6, 0xcf9);
- halt();
- }
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
- if (boot_mode == 0) {
+void mainboard_early_init(int s3resume)
+{
+ if (!s3resume) {
/* This is the fastest way to let users know
* the Intel CPU is now alive.
*/
google_chromeec_kbbacklight(100);
}
+}
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- /* Prepare USB controller early in S3 resume */
- if (boot_mode == 2)
- enable_usb_bar();
-
- post_code(0x39);
-
- copy_spd(&pei_data);
-
- post_code(0x3a);
- pei_data.boot_mode = boot_mode;
- timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(&pei_data);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- quick_ram_check();
- post_code(0x3e);
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
- if (boot_mode!=2)
- save_mrc_data(&pei_data);
-
- if (boot_mode==2 && !cbmem_was_initted) {
- /* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- halt();
- }
- northbridge_romstage_finalize(boot_mode==2);
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
- post_code(0x3f);
- if (CONFIG_LPC_TPM) {
- init_tpm(boot_mode == 2);
- }
+void mainboard_config_superio(void)
+{
}
diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h
index 1cfd487f09..c3e3e2fbe7 100644
--- a/src/mainboard/google/parrot/gpio.h
+++ b/src/mainboard/google/parrot/gpio.h
@@ -254,7 +254,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_LOW,
};
-const struct pch_gpio_map parrot_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 029805b045..60c3f010f8 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -31,7 +31,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <halt.h>
#include "gpio.h"
@@ -39,7 +38,7 @@
#include <tpm.h>
#include "ec/compal/ene932/ec.h"
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* Parrot EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -52,7 +51,7 @@ static void pch_enable_lpc(void)
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
}
-static void rcba_config(void)
+void rcba_config(void)
{
u32 reg32;
@@ -107,13 +106,13 @@ static void rcba_config(void)
RCBA32(FD) = reg32;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_early_init(int s3resume)
{
- int boot_mode = 0;
- int cbmem_was_initted;
+}
- struct pei_data pei_data = {
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -158,81 +157,14 @@ void main(unsigned long bist)
{ 0, 4, 0x0000 }, /* P13: Empty */
},
};
+ *pei_data = pei_data_template;
+}
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
- setup_pch_gpios(&parrot_gpio_map);
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- printk(BIOS_DEBUG, "soft reset detected\n");
- boot_mode = 1;
-
- /* System is not happy after keyboard reset... */
- printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
- outb(0x6, 0xcf9);
- halt();
- }
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- /* Prepare USB controller early in S3 resume */
- if (boot_mode == 2)
- enable_usb_bar();
-
- post_code(0x39);
-
- post_code(0x3a);
- pei_data.boot_mode = boot_mode;
- timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(&pei_data);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- quick_ram_check();
- post_code(0x3e);
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
- if (boot_mode!=2)
- save_mrc_data(&pei_data);
-
- if (boot_mode==2 && !cbmem_was_initted) {
- /* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- halt();
- }
- northbridge_romstage_finalize(boot_mode==2);
+void mainboard_config_superio(void)
+{
+}
- post_code(0x3f);
- if (CONFIG_LPC_TPM) {
- init_tpm(boot_mode == 2);
- }
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
}
diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h
index f992013519..7fffe8b48b 100644
--- a/src/mainboard/google/stout/gpio.h
+++ b/src/mainboard/google/stout/gpio.h
@@ -267,7 +267,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio72 = GPIO_LEVEL_HIGH,
};
-const struct pch_gpio_map stout_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 030dee75ff..99979e9e90 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -31,7 +31,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <halt.h>
#include "gpio.h"
@@ -42,7 +41,7 @@
#include "ec.h"
#include "onboard.h"
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/*
* Enable:
@@ -58,7 +57,7 @@ static void pch_enable_lpc(void)
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
}
-static void rcba_config(void)
+void rcba_config(void)
{
u32 reg32;
@@ -113,13 +112,6 @@ static void rcba_config(void)
RCBA32(FD) = reg32;
}
-// FIXME, this function is generic code that should go to sb/... or
-// nb/../early_init.c
-static void early_pch_init(void)
-{
- // Nothing to do for stout
-}
-
/*
* The Stout EC needs to be reset to RW mode. It is important that
* the RTC_PWR_STS is not set until ramstage EC init.
@@ -148,13 +140,9 @@ static void early_ec_init(void)
}
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- int boot_mode = 0;
- int cbmem_was_initted;
-
- struct pei_data pei_data = {
+ struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -204,89 +192,22 @@ void main(unsigned long bist)
.xhci_streams = XHCI_STREAMS,
},
};
+ *pei_data = pei_data_template;
+}
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
- setup_pch_gpios(&stout_gpio_map);
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- printk(BIOS_DEBUG, "soft reset detected\n");
- boot_mode = 1;
-
- /* System is not happy after keyboard reset... */
- printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
- outb(0x6, 0xcf9);
- halt();
- }
-
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
-
+void mainboard_early_init(int s3resume)
+{
/* Do ec reset as early as possible, but skip it on S3 resume */
- if (boot_mode < 2)
+ if (!s3resume) {
early_ec_init();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- /* Prepare USB controller early in S3 resume */
- if (boot_mode == 2)
- enable_usb_bar();
-
- post_code(0x39);
-
- post_code(0x3a);
- pei_data.boot_mode = boot_mode;
- timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_initialize(&pei_data);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3b);
- /* Perform some initialization that must run before stage2 */
- early_pch_init();
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- quick_ram_check();
- post_code(0x3e);
-
- cbmem_was_initted = !cbmem_recovery(boot_mode==2);
- if (boot_mode!=2)
- save_mrc_data(&pei_data);
-
- if (boot_mode==2 && !cbmem_was_initted) {
- /* Failed S3 resume, reset to come up cleanly */
- outb(0x6, 0xcf9);
- halt();
}
- northbridge_romstage_finalize(boot_mode==2);
+}
- post_code(0x3f);
- if (CONFIG_LPC_TPM) {
- init_tpm(boot_mode == 2);
- }
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+
+void mainboard_config_superio(void)
+{
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 10:17:28 +0000