diff options
Diffstat (limited to 'src/mainboard/google')
18 files changed, 537 insertions, 566 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index f5e5fb6b6d..7a4ed08f59 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct lpddr4x_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); void variant_memory_init(FSP_M_CONFIG *mem_cfg); /* SKU ID structure */ diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index 2184f9b16f..09e0987ed9 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -5,56 +5,76 @@ #include <gpio.h> #include <soc/romstage.h> -static const struct mb_ddr4_cfg baseboard_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, + /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */ - { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */ - { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ - { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */ - { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ - { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ - { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ - { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ + .ddr4_dq_map = { + .ddr0 = { + .dq0 = { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */ + .dq1 = { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */ + .dq2 = { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */ + .dq3 = { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */ + .dq4 = { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */ + .dq5 = { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */ + .dq6 = { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */ + .dq7 = { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */ }, - [1] = { - { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */ - { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ - { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ - { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ - { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ - { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ - { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ - { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ + .ddr1 = { + .dq0 = { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */ + .dq1 = { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */ + .dq2 = { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */ + .dq3 = { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */ + .dq4 = { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */ + .dq5 = { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */ + .dq6 = { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */ + .dq7 = { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - { 1, 0, 1, 0, 0, 1, 1, 0 }, - { 1, 0, 1, 0, 1, 0, 1, 0 } + .ddr4_dqs_map = { + .ddr0 = { + .dqs0 = 1, + .dqs1 = 0, + .dqs2 = 1, + .dqs3 = 0, + .dqs4 = 0, + .dqs5 = 1, + .dqs6 = 1, + .dqs7 = 0, + }, + .ddr1 = { + .dqs0 = 1, + .dqs1 = 0, + .dqs2 = 1, + .dqs3 = 0, + .dqs4 = 1, + .dqs5 = 0, + .dqs6 = 1, + .dqs7 = 0, + } }, - .ect = 0, /* Disable Early Command Training */ + .ect = false, /* Disable Early Command Training */ }; void variant_memory_init(FSP_M_CONFIG *mem_cfg) { - const struct spd_info spd_info = { - .topology = SODIMM, - .smbus_info[0] = {.addr_dimm0 = 0x50, - .addr_dimm1 = 0 }, - .smbus_info[1] = {.addr_dimm0 = 0x52, - .addr_dimm1 = 0 }, + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, }; const bool half_populated = false; - struct mb_ddr4_cfg new_board_cfg_ddr4; + struct mb_cfg new_board_cfg_ddr4; memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg)); - new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); + new_board_cfg_ddr4.ddr4_config.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); - meminit_ddr4(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); + memcfg_init(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); } diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c index 68c8d0e991..f8506df54b 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/memory.c +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -5,59 +5,61 @@ #include <gpio.h> #include <variant/gpio.h> -static const struct lpddr4x_cfg baseboard_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ - { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ - { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ - { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ - { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ - { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ - { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 0, /* Early Command Training */ + .ect = false, /* Early Command Training */ }; -const struct lpddr4x_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } @@ -77,12 +79,11 @@ static int variant_memory_sku(void) void variant_memory_init(FSP_M_CONFIG *mem_cfg) { - const struct lpddr4x_cfg *board_cfg = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *board_cfg = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; const bool half_populated = false; - meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 67d3489b03..f3fb454eb3 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -14,13 +14,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct ddr_memory_cfg *board_cfg = variant_memory_params(); - const struct spd_info spd_info = { - .topology = MEMORY_DOWN, - .md_spd_loc = SPD_CBFS, + const struct mb_cfg *board_cfg = variant_memory_params(); + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = variant_memory_sku(), }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index 4d5dc87cb9..2431c59cdc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -18,7 +18,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); -const struct ddr_memory_cfg *variant_memory_params(void); +const struct mb_cfg *variant_memory_params(void); int variant_memory_sku(void); /* Modify devictree settings during ramstage. */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b3a6..1998a1fb27 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -4,64 +4,59 @@ #include <baseboard/variants.h> #include <gpio.h> -static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { - /* DQ CPU<>DRAM map */ - .dq_map = { - [0] = { - { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &baseboard_lpddr4x_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *__weak variant_memory_params(void) +const struct mb_cfg *__weak variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/copano/memory.c b/src/mainboard/google/volteer/variants/copano/memory.c index 7821157a58..b4414d4019 100644 --- a/src/mainboard/google/volteer/variants/copano/memory.c +++ b/src/mainboard/google/volteer/variants/copano/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg copano_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &copano_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 9d8ad405ce..6ccb5034d6 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -2,64 +2,59 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg delbin_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &delbin_memcfg + .ect = true, }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/drobit/memory.c b/src/mainboard/google/volteer/variants/drobit/memory.c index 9d8ad405ce..2b4ec29092 100644 --- a/src/mainboard/google/volteer/variants/drobit/memory.c +++ b/src/mainboard/google/volteer/variants/drobit/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg delbin_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &delbin_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/eldrid/memory.c b/src/mainboard/google/volteer/variants/eldrid/memory.c index 577734dbcf..04dbe4492e 100644 --- a/src/mainboard/google/volteer/variants/eldrid/memory.c +++ b/src/mainboard/google/volteer/variants/eldrid/memory.c @@ -4,16 +4,11 @@ #include <baseboard/variants.h> #include <gpio.h> -/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ -static const struct mb_ddr4_cfg eldrid_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_DDR4, - .ddr4_cfg = &eldrid_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c index 32b7abca17..8ec6996d11 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory.c +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -4,16 +4,11 @@ #include <baseboard/variants.h> #include <gpio.h> -/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ -static const struct mb_ddr4_cfg elemi_memcfg = { +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_DDR4, }; -static const struct ddr_memory_cfg baseboard_memcfg = { - .mem_type = MEMTYPE_DDR4, - .ddr4_cfg = &elemi_memcfg -}; - -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &baseboard_memcfg; } diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c index edbb681a4e..ef039a4526 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg halvor_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ + .dq1 = { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &halvor_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c index 11bcf4ca89..f9350d1471 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory.c +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -2,64 +2,60 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg lindar_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &lindar_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 2c879e09b4..f9350d1471 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -2,64 +2,60 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg malefor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &malefor_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 7d95658891..b4414d4019 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg terrador_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &terrador_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index c8b4ab4e3c..b4414d4019 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg todor_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &todor_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voema/memory.c b/src/mainboard/google/volteer/variants/voema/memory.c index b611af5161..b4414d4019 100644 --- a/src/mainboard/google/volteer/variants/voema/memory.c +++ b/src/mainboard/google/volteer/variants/voema/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg voema_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &voema_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 40b108660d..fe2b2b1999 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -2,64 +2,61 @@ #include <baseboard/variants.h> -static const struct lpddr4x_cfg voxel_memcfg = { +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ }, - [1] = { - { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ - { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + .ddr1 = { + .dq0 = { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ }, - [2] = { - { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ - { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ }, - [3] = { - { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ - { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + .ddr3 = { + .dq0 = { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ }, - [4] = { - { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ - { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + .ddr4 = { + .dq0 = { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ }, - [5] = { - { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ - { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + .ddr5 = { + .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ }, - [6] = { - { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ - { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + .ddr6 = { + .dq0 = { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ }, - [7] = { - { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ - { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + .ddr7 = { + .dq0 = { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ }, - .ect = 1, /* Enable Early Command Training */ -}; - -static const struct ddr_memory_cfg board_memcfg = { - .mem_type = MEMTYPE_LPDDR4X, - .lpddr4_cfg = &voxel_memcfg + .ect = true, /* Enable Early Command Training */ }; -const struct ddr_memory_cfg *variant_memory_params(void) +const struct mb_cfg *variant_memory_params(void) { return &board_memcfg; } |