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-rw-r--r--src/mainboard/google/reef/Kconfig53
-rw-r--r--src/mainboard/google/reef/Kconfig.name3
-rw-r--r--src/mainboard/google/reef/Makefile.inc8
-rw-r--r--src/mainboard/google/reef/acpi/chromeos.asl23
-rw-r--r--src/mainboard/google/reef/acpi/mainboard.asl16
-rw-r--r--src/mainboard/google/reef/acpi/superio.asl24
-rw-r--r--src/mainboard/google/reef/acpi_tables.c14
-rw-r--r--src/mainboard/google/reef/board_info.txt6
-rw-r--r--src/mainboard/google/reef/bootblock.c27
-rw-r--r--src/mainboard/google/reef/chromeos.c71
-rw-r--r--src/mainboard/google/reef/chromeos.fmd40
-rw-r--r--src/mainboard/google/reef/devicetree.cb56
-rw-r--r--src/mainboard/google/reef/dsdt.asl45
-rw-r--r--src/mainboard/google/reef/ec.c70
-rw-r--r--src/mainboard/google/reef/ec.h60
-rw-r--r--src/mainboard/google/reef/gpio.h29
-rw-r--r--src/mainboard/google/reef/mainboard.c29
-rw-r--r--src/mainboard/google/reef/romstage.c74
18 files changed, 648 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
new file mode 100644
index 0000000000..e49e8b6b75
--- /dev/null
+++ b/src/mainboard/google/reef/Kconfig
@@ -0,0 +1,53 @@
+if BOARD_GOOGLE_REEF
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_APOLLOLAKE
+ # FIXME(adurbin): this SPI part is really 16MiB
+ select BOARD_ROMSIZE_KB_8192
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_LPC
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+ select SYSTEM_TYPE_LAPTOP
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 0
+
+config IFD_BIOS_END
+ hex
+ default 0x6FF000
+
+config IFD_BIOS_START
+ hex
+ default 0x1000
+
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+ select CHROMEOS_VBNV_CMOS
+ select CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH
+ select EC_SOFTWARE_SYNC
+ select LID_SWITCH
+ select VBOOT_OPROM_MATTERS
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/reef
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Reef"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Reef"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif # BOARD_GOOGLE_REEF
diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name
new file mode 100644
index 0000000000..ba31f2f46d
--- /dev/null
+++ b/src/mainboard/google/reef/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_GOOGLE_REEF
+ bool "Reef"
+
diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc
new file mode 100644
index 0000000000..b38a4e6488
--- /dev/null
+++ b/src/mainboard/google/reef/Makefile.inc
@@ -0,0 +1,8 @@
+bootblock-y += bootblock.c
+bootblock-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/reef/acpi/chromeos.asl b/src/mainboard/google/reef/acpi/chromeos.asl
new file mode 100644
index 0000000000..d6a00807c8
--- /dev/null
+++ b/src/mainboard/google/reef/acpi/chromeos.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio_defs.h>
+
+Name (OIPG, Package () {
+ /* No physical recovery GPIO. */
+ Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:00" },
+ /* Firmware write protect GPIO. */
+ Package () { 0x0003, 1, GPIO_75, "INT3452:00" },
+})
diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl
new file mode 100644
index 0000000000..05ea06add3
--- /dev/null
+++ b/src/mainboard/google/reef/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "acpi/superio.asl"
diff --git a/src/mainboard/google/reef/acpi/superio.asl b/src/mainboard/google/reef/acpi/superio.asl
new file mode 100644
index 0000000000..d8ceddb4c8
--- /dev/null
+++ b/src/mainboard/google/reef/acpi/superio.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/reef/acpi_tables.c b/src/mainboard/google/reef/acpi_tables.c
new file mode 100644
index 0000000000..8d4d1cf7e7
--- /dev/null
+++ b/src/mainboard/google/reef/acpi_tables.c
@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/mainboard/google/reef/board_info.txt b/src/mainboard/google/reef/board_info.txt
new file mode 100644
index 0000000000..9b1f2a4fdb
--- /dev/null
+++ b/src/mainboard/google/reef/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Reef Apollolake Reference Board
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c
new file mode 100644
index 0000000000..56af987467
--- /dev/null
+++ b/src/mainboard/google/reef/bootblock.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/lpc.h>
+#include <soc/gpio.h>
+#include "ec.h"
+#include "gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+ lpc_configure_pads();
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+ mainboard_ec_init();
+}
diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c
new file mode 100644
index 0000000000..4de6a70ce9
--- /dev/null
+++ b/src/mainboard/google/reef/chromeos.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/gpio.h>
+#include "ec.h"
+
+#define GPIO_PCH_WP GPIO_75
+#define GPIO_EC_IN_RW GPIO_41
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH,
+ gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_lid_switch(void)
+{
+ /* Read lid switch state from the EC. */
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+}
+
+int get_developer_mode_switch(void)
+{
+ /* No physical developer mode switch. It's virtual. */
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ /* Check if the EC has posted the keyboard recovery event. */
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int clear_recovery_mode_switch(void)
+{
+ /* Clear keyboard recovery event. */
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd
new file mode 100644
index 0000000000..5e8b559795
--- /dev/null
+++ b/src/mainboard/google/reef/chromeos.fmd
@@ -0,0 +1,40 @@
+FLASH 8M {
+ WP_RO 4M {
+ SI_ALL 2M {
+ SI_DESC 4K
+ bootblock@509056 32K
+ }
+ RO_SECTION@2M 2M {
+ RO_VPD 0x4000
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_FRID_PAD 0x7c0
+ COREBOOT(CBFS)
+ # logical boot partition 2. Remove with updated CSE
+ SIGN_CSE@0x180000 64K
+ # GBB grows to fill the remaining region...
+ GBB
+ }
+ }
+ MISC_RW {
+ RW_MRC_CACHE 64K
+ RW_ELOG 16K
+ RW_SHARED 16K {
+ SHARED_DATA 8K
+ VBLOCK_DEV 8K
+ }
+ RW_VPD 8K
+ }
+ RW_SECTION_A 0xf0000 {
+ VBLOCK_A 64K
+ FW_MAIN_A(CBFS) 768K
+ RW_FWID_A 64
+ }
+ RW_SECTION_B 0xf0000 {
+ VBLOCK_B 64K
+ FW_MAIN_B(CBFS) 768K
+ RW_FWID_B 64
+ }
+ DEVICE_EXTENSION@7M 1M
+}
+
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
new file mode 100644
index 0000000000..f442872bd3
--- /dev/null
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -0,0 +1,56 @@
+chip soc/intel/apollolake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
+
+ device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 11.0 on end # - ISH
+ device pci 12.0 off end # - SATA
+ device pci 13.0 off end # - Root Port 2 - PCIe-A 0
+ device pci 13.1 off end # - Root Port 3 - PCIe-A 1
+ device pci 13.2 off end # - Root Port 4 - PCIe-A 2
+ device pci 13.3 off end # - Root Port 5 - PCIe-A 3
+ device pci 14.0 on end # - Root Port 0 - PCIe-B 0 - Wifi
+ device pci 14.1 off end # - Root Port 1 - PCIe-B 1
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 on end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 on end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 on end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1b.0 on end # - SDCARD
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 on end # - SDIO
+ device pci 1f.0 on # - LPC
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
+ device pci 1f.1 on end # - SMBUS
+ end
+end
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
new file mode 100644
index 0000000000..41bb523f85
--- /dev/null
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ /* global NVS and variables */
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/apollolake/acpi/northbridge.asl>
+ #include <soc/intel/apollolake/acpi/southbridge.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+ /* Mainboard Specific devices */
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c
new file mode 100644
index 0000000000..fd35eedcfc
--- /dev/null
+++ b/src/mainboard/google/reef/ec.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <rules.h>
+#include <soc/lpc.h>
+#include "ec.h"
+
+static void ramstage_ec_init(void)
+{
+ printk(BIOS_ERR, "mainboard: EC init\n");
+
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0)
+ ;
+
+ /* Restore SCI event mask */
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake event mask */
+ google_chromeec_set_wake_mask(0);
+}
+
+static void bootblock_ec_init(void)
+{
+ uint16_t ec_ioport_base;
+ size_t ec_ioport_size;
+
+ /*
+ * Set up LPC decoding for the ChromeEC I/O port ranges:
+ * - Ports 62/66, 60/64, and 200->208
+ * - ChromeEC specific communication I/O ports.
+ */
+ lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+ google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+ lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
+}
+
+void mainboard_ec_init(void)
+{
+ if (ENV_RAMSTAGE)
+ ramstage_ec_init();
+ else if (ENV_BOOTBLOCK)
+ bootblock_ec_init();
+}
diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h
new file mode 100644
index 0000000000..51d4028aa5
--- /dev/null
+++ b/src/mainboard/google/reef/ec.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
new file mode 100644
index 0000000000..fb1724256d
--- /dev/null
+++ b/src/mainboard/google/reef/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+};
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+};
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c
new file mode 100644
index 0000000000..31bf9c8ca7
--- /dev/null
+++ b/src/mainboard/google/reef/mainboard.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <soc/gpio.h>
+#include "ec.h"
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+ mainboard_ec_init();
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+};
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
new file mode 100644
index 0000000000..ecf6fa502d
--- /dev/null
+++ b/src/mainboard/google/reef/romstage.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct lpddr4_swizzle_cfg board_swizzle = {
+ /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
+ .phys[LP4_PHYS_CH0A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 },
+ },
+ .phys[LP4_PHYS_CH0B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 },
+ },
+ .phys[LP4_PHYS_CH1A] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 },
+ },
+ .phys[LP4_PHYS_CH1B] = {
+ /* DQA[0:7] pins of LPDDR4 module. */
+ .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 },
+ /* DQA[8:15] pins of LPDDR4 module. */
+ .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 },
+ /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 },
+ /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
+ .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 },
+ },
+};
+
+void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+{
+ struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
+
+ /* Use a default 2400 speed. */
+ meminit_lpddr4(cfg, LP4_SPEED_2400);
+ /* Enable both logical channels with a 8Gb density. */
+ meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY,
+ &board_swizzle);
+ meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY,
+ &board_swizzle);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 02:54:22 +0000