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-rw-r--r--src/mainboard/google/guybrush/mainboard.c48
-rw-r--r--src/mainboard/google/kahlee/mainboard.c41
-rw-r--r--src/mainboard/google/skyrim/mainboard.c48
-rw-r--r--src/mainboard/google/zork/mainboard.c50
4 files changed, 12 insertions, 175 deletions
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 8deb2ac76b..a7eab0804b 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -12,7 +12,6 @@
#include <gpio.h>
#include <soc/acpi.h>
#include <variant/ec.h>
-#include <string.h>
#define BACKLIGHT_GPIO GPIO_129
#define WWAN_AUX_RST_GPIO GPIO_18
@@ -23,16 +22,8 @@
#define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
#define METHOD_MAINBOARD_S0X "\\_SB.MS0X"
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
@@ -74,41 +65,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_HPET_H, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_configure_gpios(void)
{
size_t base_num_gpios, override_num_gpios;
@@ -219,10 +181,6 @@ static void mainboard_enable(struct device *dev)
dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-
/* TODO: b/184678786 - Move into espi_config */
/* Unmask eSPI IRQ 1 (Keyboard) */
pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 3433f8bcaa..9cbfd4be46 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -18,17 +18,8 @@
#include <variant/ec.h>
#include <variant/thermal.h>
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_A, 3, 16 },
{ PIRQ_B, 4, 17 },
@@ -61,35 +52,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_MISC2, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
/*
* This table defines the index into the picr/intr_data tables for each
* device. Any enabled device and slot that uses hardware interrupts should
@@ -117,8 +85,6 @@ static void pirq_setup(void)
{
pirq_data_ptr = mainboard_pirq_data;
pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
}
void __weak variant_devtree_update(void)
@@ -165,7 +131,6 @@ static void mainboard_init(void *chip_info)
*************************************************/
static void mainboard_enable(struct device *dev)
{
- init_tables();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c
index ca3c9aa2d1..7708488554 100644
--- a/src/mainboard/google/skyrim/mainboard.c
+++ b/src/mainboard/google/skyrim/mainboard.c
@@ -6,19 +6,10 @@
#include <console/console.h>
#include <device/device.h>
#include <soc/acpi.h>
-#include <string.h>
#include <variant/ec.h>
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
@@ -60,41 +51,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_HPET_H, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_configure_gpios(void)
{
size_t base_num_gpios, override_num_gpios;
@@ -117,10 +79,6 @@ static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-
/* TODO: b/184678786 - Move into espi_config */
/* Unmask eSPI IRQ 1 (Keyboard) */
pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index aaa254893e..90c74d7e4e 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <string.h>
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
@@ -31,16 +30,8 @@
#define METHOD_MAINBOARD_WAK "\\_SB.MWAK"
#define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system. It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair. These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
/*
* This controls the device -> IRQ routing.
@@ -78,42 +69,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
{ PIRQ_MISC2, 0x00, 0x00 },
};
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
{
*length = ARRAY_SIZE(fch_irq_map);
return fch_irq_map;
}
-static void init_tables(void)
-{
- const struct fch_irq_routing *mb_irq_map;
- size_t mb_fch_irq_mapping_table_size;
- size_t i;
-
- mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
- memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
- memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
- for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
- if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
- printk(BIOS_WARNING,
- "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
- mb_irq_map[i].intr_index, i);
- continue;
- }
- fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
- fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
- }
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
- intr_data_ptr = fch_apic_routing;
- picr_data_ptr = fch_pic_routing;
-}
-
static void mainboard_configure_gpios(void)
{
size_t base_num_gpios, override_num_gpios;
@@ -205,12 +166,7 @@ static void mainboard_fill_ssdt(const struct device *dev)
*************************************************/
static void mainboard_enable(struct device *dev)
{
- init_tables();
- /* Initialize the PIRQ data structures for consumption */
- pirq_setup();
-
dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
-
}
static void mainboard_final(void *chip_info)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 22:12:19 +0000