diff options
Diffstat (limited to 'src/mainboard/google')
25 files changed, 0 insertions, 2141 deletions
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig deleted file mode 100644 index af4c68cd3a..0000000000 --- a/src/mainboard/google/panther/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -if BOARD_GOOGLE_PANTHER - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_HASWELL - select NORTHBRIDGE_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT - select INTEL_LYNXPOINT_LP - select BOARD_ROMSIZE_KB_8192 - select SUPERIO_ITE_IT8772F - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select INTEL_INT15 - -config CHROMEOS - select PHYSICAL_REC_SWITCH - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/panther - -config MAINBOARD_PART_NUMBER - string - default "Panther" - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config GBB_HWID - string - depends on CHROMEOS - default "X86 PANTHER TEST 6287" -endif diff --git a/src/mainboard/google/panther/Kconfig.name b/src/mainboard/google/panther/Kconfig.name deleted file mode 100644 index c8cd14b3be..0000000000 --- a/src/mainboard/google/panther/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_PANTHER - bool "Panther" diff --git a/src/mainboard/google/panther/Makefile.inc b/src/mainboard/google/panther/Makefile.inc deleted file mode 100644 index ab4dcc054a..0000000000 --- a/src/mainboard/google/panther/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += chromeos.c -ramstage-y += chromeos.c -ramstage-y += lan.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/panther/acpi/ec.asl b/src/mainboard/google/panther/acpi/ec.asl deleted file mode 100644 index e69de29bb2..0000000000 --- a/src/mainboard/google/panther/acpi/ec.asl +++ /dev/null diff --git a/src/mainboard/google/panther/acpi/haswell_pci_irqs.asl b/src/mainboard/google/panther/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9839..0000000000 --- a/src/mainboard/google/panther/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl deleted file mode 100644 index d7cd12dd5e..0000000000 --- a/src/mainboard/google/panther/acpi/mainboard.asl +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/panther/onboard.h> - -Scope (\_SB) -{ - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } -} - -/* - * LAN connected to Root Port 3, becomes Root Port 1 after coalesce - */ -Scope (\_SB.PCI0.RP01) -{ - Device (ETH0) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (PANTHER_NIC_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) - } - } - } -} - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (PANTHER_WLAN_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) - } - } - } -} diff --git a/src/mainboard/google/panther/acpi/platform.asl b/src/mainboard/google/panther/acpi/platform.asl deleted file mode 100644 index bc2fba2ff1..0000000000 --- a/src/mainboard/google/panther/acpi/platform.asl +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Initialize thermal defaults */ - \_TZ.THRM._INI () - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/panther/acpi/superio.asl b/src/mainboard/google/panther/acpi/superio.asl deleted file mode 100644 index 6fa388c21d..0000000000 --- a/src/mainboard/google/panther/acpi/superio.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Values should match those defined in devicetree.cb */ - -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR - -#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 - -#include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/google/panther/acpi/thermal.asl b/src/mainboard/google/panther/acpi/thermal.asl deleted file mode 100644 index 9fe77daa71..0000000000 --- a/src/mainboard/google/panther/acpi/thermal.asl +++ /dev/null @@ -1,337 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - // Start fan at state 4 = lowest temp state - Method (_INI) - { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - - Method (TCHK, 0, Serialized) - { - // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) - - // Check for "no reading available" - If (LEqual (Local0, 0x80)) { - Return (CTOK (\F0ON)) - } - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Return (CTOK (\F0ON)) - } - - // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) - - // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { - Return (CTOK (\TMAX)) - } - - // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) - Return (CTOK (Local0)) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for SuperIO to re-poll - Sleep (1000) - - // Re-read temperature from SuperIO - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (\F0OF)) - } Else { - Return (CTOK (\F0ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (\F1OF)) - } Else { - Return (CTOK (\F1ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (\F2OF)) - } Else { - Return (CTOK (\F2ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (\F3OF)) - } Else { - Return (CTOK (\F3ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (\F4OF)) - } Else { - Return (CTOK (\F4ON)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (\F0PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (1, \FLVL) - Store (\F1PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (\F1PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (2, \FLVL) - Store (\F2PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (\F2PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (3, \FLVL) - Store (\F3PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (\F3PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (\F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (\F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - Method (_OFF) { - If (_STA ()) { - Store (4, \FLVL) - Store (\F4PW, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) - Notify (\_TZ.THRM, 0x81) - } - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c deleted file mode 100644 index 3a015b2c62..0000000000 --- a/src/mainboard/google/panther/acpi_tables.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <string.h> -#include <types.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <ec/google/chromeec/ec.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; - gnvs->f4pw = FAN4_PWM; - - gnvs->f3of = FAN3_THRESHOLD_OFF; - gnvs->f3on = FAN3_THRESHOLD_ON; - gnvs->f3pw = FAN3_PWM; - - gnvs->f2of = FAN2_THRESHOLD_OFF; - gnvs->f2on = FAN2_THRESHOLD_ON; - gnvs->f2pw = FAN2_PWM; - - gnvs->f1of = FAN1_THRESHOLD_OFF; - gnvs->f1on = FAN1_THRESHOLD_ON; - gnvs->f1pw = FAN1_PWM; - - gnvs->f0of = FAN0_THRESHOLD_OFF; - gnvs->f0on = FAN0_THRESHOLD_ON; - gnvs->f0pw = FAN0_PWM; - - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 5; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 1; - - -#if CONFIG_CHROMEOS - // SuperIO is always RO - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/google/panther/board_info.txt b/src/mainboard/google/panther/board_info.txt deleted file mode 100644 index 7dbef2edb5..0000000000 --- a/src/mainboard/google/panther/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: Asus -Board name: Chromebox -Category: half -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c deleted file mode 100644 index 4ee6810c8d..0000000000 --- a/src/mainboard/google/panther/chromeos.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/io.h> -#include <bootmode.h> -#include <device/device.h> -#include <device/pci.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 -#define FLAG_DEV_MODE 2 - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, 1, "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - device_t dev; -#ifdef __PRE_RAM__ - dev = PCI_DEV(0, 0x1f, 2); -#else - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -#ifdef __PRE_RAM__ -void init_bootmode_straps(void) -{ - u32 flags = 0; - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -} -#endif - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/panther/chromeos.fmd b/src/mainboard/google/panther/chromeos.fmd deleted file mode 100644 index 0c05ce95ce..0000000000 --- a/src/mainboard/google/panther/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x6f000 - COREBOOT(CBFS)@0x70000 0x180000 - } - } - } -} diff --git a/src/mainboard/google/panther/cmos.layout b/src/mainboard/google/panther/cmos.layout deleted file mode 100644 index b575e02970..0000000000 --- a/src/mainboard/google/panther/cmos.layout +++ /dev/null @@ -1,110 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb deleted file mode 100644 index af6043f52c..0000000000 --- a/src/mainboard/google/panther/devicetree.cb +++ /dev/null @@ -1,143 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Disable eDP Hotplug - register "gpu_dp_d_hotplug" = "0x00" - - # Enable DisplayPort C Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Enable FAN2 - register "fan2_enable" = "1" - - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 on - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 on - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl deleted file mode 100644 index 66cc041caa..0000000000 --- a/src/mainboard/google/panther/dsdt.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define ENABLE_TPM - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - // Mainboard devices - #include "acpi/mainboard.asl" - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> -} diff --git a/src/mainboard/google/panther/fadt.c b/src/mainboard/google/panther/fadt.c deleted file mode 100644 index 877a4b3dfc..0000000000 --- a/src/mainboard/google/panther/fadt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> -#include <device/pci.h> -#include <southbridge/intel/lynxpoint/pch.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h deleted file mode 100644 index 9f91262d1b..0000000000 --- a/src/mainboard/google/panther/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PANTHER_GPIO_H -#define PANTHER_GPIO_H - -struct pch_lp_gpio_map; - -const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_UNUSED, /* 0: UNUSED */ - LP_GPIO_UNUSED, /* 1: UNUSED */ - LP_GPIO_UNUSED, /* 2: UNUSED */ - LP_GPIO_UNUSED, /* 3: UNUSED */ - LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - LP_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ - LP_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ - LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - LP_GPIO_UNUSED, /* 11: SMBALERT */ - LP_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ - LP_GPIO_UNUSED, /* 13: UNUSED */ - LP_GPIO_UNUSED, /* 14: UNUSED */ - LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 16: UNUSED */ - LP_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ - LP_GPIO_UNUSED, /* 18: UNUSED */ - LP_GPIO_UNUSED, /* 19: UNUSED */ - LP_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ - LP_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ - LP_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ - LP_GPIO_UNUSED, /* 23: UNUSED */ - LP_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ - LP_GPIO_UNUSED, /* 25: UNUSED */ - LP_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ - LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ - LP_GPIO_UNUSED, /* 29: UNUSED */ - LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ - LP_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ - LP_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - LP_GPIO_UNUSED, /* 37: UNUSED */ - LP_GPIO_UNUSED, /* 38: UNUSED */ - LP_GPIO_UNUSED, /* 39: UNUSED */ - LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - LP_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ - LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - LP_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - LP_GPIO_UNUSED, /* 44: UNUSED */ - LP_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ - LP_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ - LP_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ - LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_UNUSED, /* 49: UNUSED */ - LP_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ - LP_GPIO_UNUSED, /* 51: UNUSED */ - LP_GPIO_UNUSED, /* 52: UNUSED */ - LP_GPIO_UNUSED, /* 53: UNUSED */ - LP_GPIO_UNUSED, /* 54: UNUSED */ - LP_GPIO_UNUSED, /* 55: UNUSED */ - LP_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ - LP_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ - LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - LP_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ - LP_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ - LP_GPIO_UNUSED, /* 61: UNUSED */ - LP_GPIO_UNUSED, /* 62: UNUSED */ - LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - LP_GPIO_UNUSED, /* 64: UNUSED */ - LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 67: UNUSED */ - LP_GPIO_UNUSED, /* 68: UNUSED */ - LP_GPIO_UNUSED, /* 69: UNUSED */ - LP_GPIO_UNUSED, /* 70: UNUSED */ - LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - LP_GPIO_UNUSED, /* 72: UNUSED */ - LP_GPIO_UNUSED, /* 73: UNUSED */ - LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - LP_GPIO_UNUSED, /* 76: UNUSED */ - LP_GPIO_UNUSED, /* 77: UNUSED */ - LP_GPIO_UNUSED, /* 78: UNUSED */ - LP_GPIO_UNUSED, /* 79: UNUSED */ - LP_GPIO_UNUSED, /* 80: UNUSED */ - LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - LP_GPIO_UNUSED, /* 83: UNUSED */ - LP_GPIO_UNUSED, /* 84: UNUSED */ - LP_GPIO_UNUSED, /* 85: UNUSED */ - LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 87: UNUSED */ - LP_GPIO_UNUSED, /* 88: UNUSED */ - LP_GPIO_UNUSED, /* 89: UNUSED */ - LP_GPIO_UNUSED, /* 90: UNUSED */ - LP_GPIO_UNUSED, /* 91: UNUSED */ - LP_GPIO_UNUSED, /* 92: UNUSED */ - LP_GPIO_UNUSED, /* 93: UNUSED */ - LP_GPIO_UNUSED, /* 94: UNUSED */ - LP_GPIO_END -}; - -#endif /* PANTHER_GPIO_H */ diff --git a/src/mainboard/google/panther/hda_verb.c b/src/mainboard/google/panther/hda_verb.c deleted file mode 100644 index da8a0c50f2..0000000000 --- a/src/mainboard/google/panther/hda_verb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include <stdlib.h> - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 - 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - AZALIA_SUBVENDOR(0x0, 0x10ec0283), - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) DMIC */ - AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - AZALIA_PIN_CFG(0x0, 0x14, 0x401111f0), - - /* Pin Complex (NID 0x17) */ - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - // group 1, cap 1 - // black, jack detect - // mic in, analog - // connector, left panel - AZALIA_PIN_CFG(0x0, 0x19, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* Pin Complex (NID 0x1d) PCBeep */ - // eapd low on ex-amp, laptop, custom enable - // mute spkr on hpout - // pcbeep en able, checksum - // no physical, internal - AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - - /* Pin Complex (NID 0x21) HPOUT PORT-I */ - // group1, - // black, jack detect - // HPOut, 1/8 stereo - // connector, left panel - AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), - - /* Undocumented settings from Realtek (needed for beep_gen) */ - /* Widget node 0x20 */ - 0x02050010, - 0x02040c20, - 0x0205001b, - 0x0204081b, -}; - -const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ - 0x01470740, /* enable speaker out */ - 0x01470c02, /* set speaker EAPD pin */ - 0x0143b01f, /* unmute speaker */ - 0x00c37100, /* unmute mixer nid 0xc input 1 */ - 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ -}; - - -#endif /* HDA_VERB_H */ -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c deleted file mode 100644 index dc6541937a..0000000000 --- a/src/mainboard/google/panther/lan.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <string.h> -#include <types.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <fmap.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "onboard.h" - -static unsigned int search(char *p, u8 *a, unsigned int lengthp, - unsigned int lengtha) -{ - int i, j; - - /* Searching */ - for (j = 0; j <= lengtha - lengthp; j++) { - for (i = 0; i < lengthp && p[i] == a[i + j]; i++) - ; - if (i >= lengthp) - return j; - } - return lengtha; -} - -static unsigned char get_hex_digit(u8 *offset) -{ - unsigned char retval = 0; - - retval = *offset - '0'; - if (retval > 0x09) { - retval = *offset - 'A' + 0x0A; - if (retval > 0x0F) - retval = *offset - 'a' + 0x0a; - } - if (retval > 0x0F) { - printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", - *offset, *offset); - retval = 0; - } - - return retval; -} - -static int get_mac_address(u32 *high_dword, u32 *low_dword, - u8 *search_address, u32 search_length) -{ - char key[] = "ethernet_mac"; - unsigned int offset; - int i; - - offset = search(key, search_address, sizeof(key) - 1, search_length); - if (offset == search_length) { - printk(BIOS_DEBUG, - "Error: Could not locate '%s' in VPD\n", key); - return 0; - } - printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); - - offset += sizeof(key); /* move to next character */ - *high_dword = 0; - - /* Fetch the MAC address and put the octets in the correct order to - * be programmed. - * - * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 - * If the MAC address is 001122334455h: - * Write 33221100h to I/O register offset 0x00 via double word access - * Write 00005544h to I/O register offset 0x04 via double word access - */ - - for (i = 0; i < 4; i++) { - *high_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *high_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - *low_dword = 0; - for (i = 0; i < 2; i++) { - *low_dword |= (get_hex_digit(search_address + offset) - << (4 + (i * 8))); - *low_dword |= (get_hex_digit(search_address + offset + 1) - << (i * 8)); - offset += 3; - } - - return *high_dword | *low_dword; -} - -static void program_mac_address(u16 io_base) -{ - void *search_address = NULL; - size_t search_length = -1; - - /* Default MAC Address of A0:00:BA:D0:0B:AD */ - u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ - u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } - } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); - } - - if (search_address == NULL) - printk(BIOS_ERR, "LAN: VPD not found.\n"); - else - get_mac_address(&high_dword, &low_dword, search_address, - search_length); - - if (io_base) { - printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); - printk(BIOS_DEBUG, "Programming MAC Address\n"); - - /* Disable register protection */ - outb(0xc0, io_base + 0x50); - outl(high_dword, io_base); - outl(low_dword, io_base + 0x04); - outb(0x60, io_base + 54); - /* Enable register protection again */ - outb(0x00, io_base + 0x50); - } -} - -void lan_init(void) -{ - u16 io_base = 0; - struct device *ethernet_dev = NULL; - - /* Get NIC's IO base address */ - ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID, - PANTHER_NIC_DEVICE_ID, 0); - if (ethernet_dev != NULL) { - io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; - - /* - * Battery life time - LAN PCIe should enter ASPM L1 to save - * power when LAN connection is idle. - * enable CLKREQ: LAN pci config space 0x81h=01 - */ - pci_write_config8(ethernet_dev, 0x81, 0x01); - } - - if (io_base) { - /* Program MAC address based on VPD data */ - program_mac_address(io_base); - - /* - * Program NIC LEDS - * - * RTL8105E Series EEPROM-Less Application Note, - * Section 5.6 LED Mode Configuration - * - * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' - * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) - * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' - */ - outb(0xc0, io_base + 0x50); /* Disable protection */ - outb((PANTHER_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); - outb(0x00, io_base + 0x50); /* Enable register protection */ - } -} diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c deleted file mode 100644 index 661e507182..0000000000 --- a/src/mainboard/google/panther/mainboard.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <smbios.h> -#include <string.h> -#include <types.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <console/console.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <drivers/intel/gma/int15.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "onboard.h" - - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - - - -static void mainboard_init(device_t dev) -{ - lan_init(); -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h deleted file mode 100644 index cacfd94a9f..0000000000 --- a/src/mainboard/google/panther/onboard.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_ONBOARD_H -#define __MAINBOARD_ONBOARD_H - -/* defines for programming the MAC address */ -#define PANTHER_NIC_VENDOR_ID 0x10EC -#define PANTHER_NIC_DEVICE_ID 0x8168 - -/* 0x00: White LINK LED and Amber ACTIVE LED */ -#define PANTHER_NIC_LED_MODE 0x00 - -/* NIC wake is GPIO 8 */ -#define PANTHER_NIC_WAKE_GPIO 8 - -/* WLAN wake is GPIO 10 */ -#define PANTHER_WLAN_WAKE_GPIO 10 - -#ifndef __ACPI__ -void lan_init(void); -#endif - -#endif /* __MAINBOARD_ONBOARD_H */ diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c deleted file mode 100644 index 7c0423ab2c..0000000000 --- a/src/mainboard/google/panther/romstage.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "gpio.h" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) -#define DUMMY_DEV PNP_DEV(0x2e, 0) - - -const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - - RCBA_END_CONFIG, -}; - -void mainboard_romstage_entry(unsigned long bist) -{ - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, - .ec_present = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - // Enable 2x refresh mode - .ddr_refresh_2x = 1, - .dq_pins_interleaved = 1, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = 1, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0064, 1, 0, /* P0: VP8 */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 0, /* P1: Port A, CN22 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 1, /* P2: Port B, CN23 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P4: Port C, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P5: Port D, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ - USB_PORT_INTERNAL }, - { 0x0000, 0, 0, /* P7: N/C */ - USB_PORT_SKIP }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; CN22 */ - { 1, 1 }, /* P2; CN23 */ - { 1, 2 }, /* P3; CN25 */ - { 1, 2 }, /* P4; CN25 */ - }, - }; - - struct romstage_params romstage_params = { - .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], - .bist = bist, - }; - - /* Early SuperIO setup */ - ite_kill_watchdog(GPIO_DEV); - it8772f_ac_resume_southbridge(DUMMY_DEV); - pch_enable_lpc(); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); -} diff --git a/src/mainboard/google/panther/smihandler.c b/src/mainboard/google/panther/smihandler.c deleted file mode 100644 index 028553772a..0000000000 --- a/src/mainboard/google/panther/smihandler.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include <cpu/x86/smm.h> -#include <northbridge/intel/haswell/haswell.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <elog.h> - -/* GPIO46 controls the WLAN_DISABLE_L signal. */ -#define GPIO_WLAN_DISABLE_L 46 -#define GPIO_LTE_DISABLE_L 59 - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - default: - break; - } - return 0; -} diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h deleted file mode 100644 index 4c7650e1ab..0000000000 --- a/src/mainboard/google/panther/thermal.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 40 -#define FAN3_THRESHOLD_ON 50 -#define FAN3_PWM 0x5a - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 58 -#define FAN2_THRESHOLD_ON 67 -#define FAN2_PWM 0xa6 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 67 -#define FAN1_THRESHOLD_ON 75 -#define FAN1_PWM 0xc0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 85 -#define FAN0_THRESHOLD_ON 90 -#define FAN0_PWM 0xff - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 98 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif /* THERMAL_H */ |