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-rw-r--r--src/mainboard/google/brya/variants/anraggar/overridetree.cb7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 8d75381d18..a95c763d1a 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -262,16 +262,17 @@ chip soc/intel/alderlake
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
- register "gpio_panel.gpio[0].gpio_num" = "GPP_F18" # EN_PP2800_WCAM_X
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
#_ON
- register "on_seq.ops_cnt" = "4"
+ register "on_seq.ops_cnt" = "5"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
- register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
+ register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
#_OFF
register "off_seq.ops_cnt" = "4"