diff options
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rambi/acpi/dptf.asl | 14 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/acpi/mainboard.asl | 14 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/acpi/thermal.asl | 245 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/acpi_tables.c | 21 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/gpio.c | 12 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/irqroute.h | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/onboard.h | 4 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/thermal.h | 32 |
10 files changed, 43 insertions, 310 deletions
diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index afb20de14b..51237dc576 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -1,16 +1,19 @@ +#define DPTF_CPU_PASSIVE 60 +#define DPTF_CPU_CRITICAL 70 + #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 40 +#define DPTF_TSR0_PASSIVE 60 #define DPTF_TSR0_CRITICAL 70 #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_PASSIVE 60 #define DPTF_TSR1_CRITICAL 70 #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 35 +#define DPTF_TSR2_PASSIVE 60 #define DPTF_TSR2_CRITICAL 70 #undef DPTF_ENABLE_CHARGER @@ -22,6 +25,11 @@ Name (DTRT, Package () { /* CPU Effect on Temp Sensor 0 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 50, 0, 0, 0, 0 }, +#endif + /* CPU Effect on Temp Sensor 1 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 501bbf7020..1f5b7a1551 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -360,3 +360,17 @@ Scope (\_SB.I2C6) Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) } } + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 14 } + + /* Mic Detect (index 1) */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 15 } + }) +} diff --git a/src/mainboard/google/rambi/acpi/thermal.asl b/src/mainboard/google/rambi/acpi/thermal.asl deleted file mode 100644 index 36310e473e..0000000000 --- a/src/mainboard/google/rambi/acpi/thermal.asl +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 0 seconds - Name (_TZP, 0) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - Method (_TMP, 0, Serialized) - { - Return (CTOK (30)) - } - - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (\F0OF)) - } Else { - Return (CTOK (\F0ON)) - } - } - - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (\F1OF)) - } Else { - Return (CTOK (\F1ON)) - } - } - - Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { - Return (CTOK (\F2OF)) - } Else { - Return (CTOK (\F2ON)) - } - } - - Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { - Return (CTOK (\F3OF)) - } Else { - Return (CTOK (\F3ON)) - } - } - - Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { - Return (CTOK (\F4OF)) - } Else { - Return (CTOK (\F4ON)) - } - } - - Name (_AL0, Package () { FAN0 }) - Name (_AL1, Package () { FAN1 }) - Name (_AL2, Package () { FAN2 }) - Name (_AL3, Package () { FAN3 }) - Name (_AL4, Package () { FAN4 }) - - PowerResource (FNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (0, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (2, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP2, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 2)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (2, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (3, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP3, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 3)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (3, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (4, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (FNP4, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 4)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (4, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (4, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - Device (FAN0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { FNP0 }) - } - - Device (FAN1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { FNP1 }) - } - - Device (FAN2) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 2) - Name (_PR0, Package () { FNP2 }) - } - - Device (FAN3) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 3) - Name (_PR0, Package () { FNP3 }) - } - - Device (FAN4) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 4) - Name (_PR0, Package () { FNP4 }) - } - } -} diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 7c0c646f67..890e1df966 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -30,19 +30,15 @@ #include <device/pci_ids.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <baytrail/acpi.h> #include <baytrail/nvs.h> #include <baytrail/iomap.h> -#include "thermal.h" - extern const unsigned char AmlCode[]; static void acpi_create_gnvs(global_nvs_t *gnvs) { - gnvs->pcnt = dev_count_cpu(); + acpi_init_gnvs(gnvs); /* Enable USB ports in S3 */ gnvs->s3u0 = 1; @@ -52,26 +48,11 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = nc_read_top_of_low_memory(); - /* TPM Present */ gnvs->tpmp = 1; /* Enable DPTF */ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tact = ACTIVE_TEMPERATURE; gnvs->dpte = 1; - -#if CONFIG_CHROMEOS - chromeos_init_vboot(&(gnvs->chromeos)); - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index fe5ec7b46a..79a2d229c0 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -33,6 +33,7 @@ chip soc/intel/baytrail # Enable devices in ACPI mode register "scc_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" # Enable PIPEA as DP_C register "gpu_pipea_hotplug" = "6" # 6ms Pulse @@ -44,6 +45,13 @@ chip soc/intel/baytrail register "gpu_pipea_light_off_delay" = "2000" # 200ms register "gpu_pipea_backlight_pwm" = "0x400" + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 4165087cd3..01b816b47d 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -35,8 +35,6 @@ DefinitionBlock( // global NVS and variables #include <soc/intel/baytrail/acpi/globalnvs.asl> - //#include "acpi/thermal.asl" - #include <soc/intel/baytrail/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index d551a15697..a3c0d2d243 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -163,9 +163,9 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { /* SSUS GPIOs */ static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ - GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ - GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */ + GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */ + GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ @@ -200,9 +200,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_NC, /* S534 - NC */ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ GPIO_NC, /* S536 - NC */ - GPIO_FUNC0, /* S537 - RAM_ID0 */ - GPIO_FUNC0, /* S538 - RAM_ID1 */ - GPIO_FUNC0, /* S539 - RAM_ID2 */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ GPIO_NC, /* S540 - NC */ GPIO_NC, /* S541 - NC */ GPIO_NC, /* S542 - NC */ diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index 733979381e..0f4ca17acc 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -19,6 +19,7 @@ #include <soc/intel/baytrail/baytrail/irq.h> #include <soc/intel/baytrail/baytrail/pci_devs.h> +#include <soc/intel/baytrail/baytrail/pmc.h> #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h index 8fb7a3f5cc..18ceca384d 100644 --- a/src/mainboard/google/rambi/onboard.h +++ b/src/mainboard/google/rambi/onboard.h @@ -24,13 +24,13 @@ #define BOARD_TRACKPAD_NAME "trackpad" #define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) -#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) #define BOARD_TRACKPAD_I2C_BUS 0 #define BOARD_TRACKPAD_I2C_ADDR 0x4b #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) -#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) #define BOARD_TOUCHSCREEN_I2C_BUS 5 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h deleted file mode 100644 index 2432b8d201..0000000000 --- a/src/mainboard/google/rambi/thermal.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef BAYLEYBAY_THERMAL_H -#define BAYLEYBAY_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 95 - -/* Passive cooling policy threshold */ -#define PASSIVE_TEMPERATURE 0 - -/* Temperature which OS will throttle CPU (when using a Fan) */ -#define ACTIVE_TEMPERATURE 80 - -#endif |