diff options
Diffstat (limited to 'src/mainboard/google')
18 files changed, 21 insertions, 21 deletions
diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 1df786db83..8e2bbe8a25 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -202,7 +202,7 @@ static void setup_storage(void) static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c0(); exynos_pinmux_i2c1(); exynos_pinmux_i2c2(); @@ -222,7 +222,7 @@ static void gpio_init(void) gpio_direction_output(GPIO_X17, 1); gpio_direction_output(GPIO_X15, 1); - /* Set up the I2S busses. */ + /* Set up the I2S buses. */ exynos_pinmux_i2s0(); exynos_pinmux_i2s1(); } diff --git a/src/mainboard/google/foster/bct/jtag.cfg b/src/mainboard/google/foster/bct/jtag.cfg index e9bbd024a5..58186b2377 100644 --- a/src/mainboard/google/foster/bct/jtag.cfg +++ b/src/mainboard/google/foster/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set DebugCtrl to 1 to reenable Jtag +# Set DebugCtrl to 1 to re-enable Jtag # DebugCtrl = 0; # diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 5dddab5584..3aafa9eeeb 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -60,7 +60,7 @@ int pwm_enum_to_pwm_number[] = { void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; - int voltage = millivolt * 10; /* for higer calculation accuracy */ + int voltage = millivolt * 10; /* for higher calculation accuracy */ int pwm_number = pwm_enum_to_pwm_number[pwm]; voltage_min = pwm_design_voltage[pwm][0]; diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 260e9340bd..381cbaaab8 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -80,7 +80,7 @@ chip soc/amd/cezanne register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f78d42096d..a84eabde5c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" - # SD card WP pin confguration + # SD card WP pin configuration register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 59c49590a3..ffec6a5396 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -117,7 +117,7 @@ static void mainboard_init(void *chip_info) gpios = variant_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); - /* Initialize i2c busses that were not initialized in bootblock */ + /* Initialize i2c buses that were not initialized in bootblock */ i2c_soc_init(); /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 1816dafc4a..728487a431 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -7,7 +7,7 @@ static void prepare_usb(void) { /* * Do DWC3 core and phy reset. Kick these resets off early - * so they get atleast 1msec to settle. + * so they get at least 1msec to settle. */ reset_usb(HSUSB_HS_PORT_1); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 0e9dc1359c..afbea9c770 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -231,7 +231,7 @@ static void display_startup(void) static void mainboard_init(struct device *dev) { /* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which - * also contains the PS8640 eDP brige and the USB hub. + * also contains the PS8640 eDP bridge and the USB hub. */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) mt6391_gpio_output(MT6391_KP_ROW2, 1); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 65bf286f08..9ffd633738 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -69,7 +69,7 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) /* * Currently we only have the case of RT5682 as the second source. And * in case of Ampton which used RT5682 as the default source, it didn't - * provide override_table right now so it will be returned ealier since + * provide override_table right now so it will be returned earlier since * table above is NULL. */ if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 85b0cc0afc..6878cadf97 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -324,7 +324,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index e6b8359996..63763b34aa 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index c279777e47..9cefb81bf8 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -330,7 +330,7 @@ static void setup_storage(void) static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c2(); exynos_pinmux_i2c4(); exynos_pinmux_i2c7(); diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 4b1254da95..d588d575dc 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -262,7 +262,7 @@ Scope (\_SB.PCI0.I2C2) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/google/smaug/bct/jtag.cfg b/src/mainboard/google/smaug/bct/jtag.cfg index 4f2c36c223..c48e54a191 100644 --- a/src/mainboard/google/smaug/bct/jtag.cfg +++ b/src/mainboard/google/smaug/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set JtagCtrl to 1 to reenable Jtag +# Set JtagCtrl to 1 to re-enable Jtag # JtagCtrl = 0; # diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 8e2d8590a6..89958c9256 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal handeler + // Thermal handler #include "acpi/thermal.asl" // global NVS and variables diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 9476723735..68eb6ea588 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ce0121593b..4bb42dea1c 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -19,7 +19,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -230,7 +230,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_OFF" diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 43ae7150dd..3f7e5d1c34 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -49,7 +49,7 @@ void variant_touchscreen_update(void); void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and - * overrideable by the variant. */ + * overridable by the variant. */ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, |